From: Alvin Chang via <qemu-riscv@nongnu.org>
To: <qemu-riscv@nongnu.org>, <qemu-devel@nongnu.org>
Cc: <alistair.francis@wdc.com>, <bin.meng@windriver.com>,
<liwei1518@gmail.com>, <dbarboza@ventanamicro.com>,
<zhiwei_liu@linux.alibaba.com>,
Alvin Chang <alvinga@andestech.com>
Subject: [PATCH v2 2/4] target/riscv: Apply modularized matching conditions for breakpoint
Date: Fri, 23 Feb 2024 10:21:17 +0800 [thread overview]
Message-ID: <20240223022119.41255-3-alvinga@andestech.com> (raw)
In-Reply-To: <20240223022119.41255-1-alvinga@andestech.com>
We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level.
Remove the related code in riscv_cpu_debug_check_breakpoint() and invoke
trigger_common_match() to check the privilege levels of the type 2 and
type 6 triggers for the breakpoints.
This commit also changes the behavior of looping the triggers. In
previous implementation, if we have a type 2 trigger and
env->virt_enabled is true, we directly return false to stop the loop.
Now we keep looping all the triggers until we find a matched trigger.
Only the execution bit and the executed PC should be futher checked in
riscv_cpu_debug_check_breakpoint().
Signed-off-by: Alvin Chang <alvinga@andestech.com>
---
target/riscv/debug.c | 26 ++++++--------------------
1 file changed, 6 insertions(+), 20 deletions(-)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 3891236b82..b7b0fa8945 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -855,21 +855,17 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
for (i = 0; i < RV_MAX_TRIGGERS; i++) {
trigger_type = get_trigger_type(env, i);
+ if (!trigger_common_match(env, trigger_type, i)) {
+ continue;
+ }
+
switch (trigger_type) {
case TRIGGER_TYPE_AD_MATCH:
- /* type 2 trigger cannot be fired in VU/VS mode */
- if (env->virt_enabled) {
- return false;
- }
-
ctrl = env->tdata1[i];
pc = env->tdata2[i];
if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
- /* check U/S/M bit against current privilege level */
- if ((ctrl >> 3) & BIT(env->priv)) {
- return true;
- }
+ return true;
}
break;
case TRIGGER_TYPE_AD_MATCH6:
@@ -877,17 +873,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
pc = env->tdata2[i];
if ((ctrl & TYPE6_EXEC) && (bp->pc == pc)) {
- if (env->virt_enabled) {
- /* check VU/VS bit against current privilege level */
- if ((ctrl >> 23) & BIT(env->priv)) {
- return true;
- }
- } else {
- /* check U/S/M bit against current privilege level */
- if ((ctrl >> 3) & BIT(env->priv)) {
- return true;
- }
- }
+ return true;
}
break;
default:
--
2.34.1
next prev parent reply other threads:[~2024-02-23 2:22 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-23 2:21 [PATCH v2 0/4] RISC-V: Modularize common match conditions for trigger Alvin Chang via
2024-02-23 2:21 ` [PATCH v2 1/4] target/riscv: Add functions for common matching conditions of trigger Alvin Chang via
2024-02-23 2:21 ` Alvin Chang via [this message]
2024-02-26 23:50 ` [PATCH v2 2/4] target/riscv: Apply modularized matching conditions for breakpoint Alistair Francis
2024-02-23 2:21 ` [PATCH v2 3/4] target/riscv: Apply modularized matching conditions for watchpoint Alvin Chang via
2024-02-23 2:21 ` [PATCH v2 4/4] target/riscv: Apply modularized matching conditions for icount trigger Alvin Chang via
2024-02-26 0:25 ` [PATCH v2 0/4] RISC-V: Modularize common match conditions for trigger Alistair Francis
2024-02-26 1:16 ` Alvin Che-Chia Chang(張哲嘉)
2024-02-26 6:44 ` Alistair Francis
2024-02-26 7:21 ` Alvin Che-Chia Chang(張哲嘉)
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