From: "demin.han" <demin.han@starfivetech.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, dbarboza@ventanamicro.com,
alistair.francis@wdc.com
Subject: [PATCH v2] target/riscv: Fix shift count overflow
Date: Sun, 25 Feb 2024 11:27:20 +0800 [thread overview]
Message-ID: <20240225032720.375078-1-demin.han@starfivetech.com> (raw)
The result of (8 - 3 - vlmul) is negtive when vlmul >= 6,
and results in wrong vill.
Signed-off-by: demin.han <demin.han@starfivetech.com>
---
target/riscv/vector_helper.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 84cec73eb2..fe56c007d5 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -44,6 +44,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
target_ulong reserved = s2 &
MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
xlen - 1 - R_VTYPE_RESERVED_SHIFT);
+ uint16_t vlen = cpu->cfg.vlenb << 3;
int8_t lmul;
if (vlmul & 4) {
@@ -53,10 +54,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
* VLEN * LMUL >= SEW
* VLEN >> (8 - lmul) >= sew
* (vlenb << 3) >> (8 - lmul) >= sew
- * vlenb >> (8 - 3 - lmul) >= sew
*/
- if (vlmul == 4 ||
- cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) {
+ if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
vill = true;
}
}
--
2.43.2
next reply other threads:[~2024-02-25 3:28 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-25 3:27 demin.han [this message]
2024-02-25 10:16 ` [PATCH v2] target/riscv: Fix shift count overflow Daniel Henrique Barboza
2024-02-25 16:49 ` Philippe Mathieu-Daudé
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