From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Max Chou <max.chou@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: [PATCH] target/riscv/vector_helper.c: Avoid shifting negative in fractional LMUL checking
Date: Thu, 7 Mar 2024 00:10:22 +0800 [thread overview]
Message-ID: <20240306161036.938931-1-max.chou@sifive.com> (raw)
When vlmul is larger than 5, the original fractional LMUL checking may
gets unexpected result.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/vector_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 84cec73eb20..adceec378fd 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -53,10 +53,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
* VLEN * LMUL >= SEW
* VLEN >> (8 - lmul) >= sew
* (vlenb << 3) >> (8 - lmul) >= sew
- * vlenb >> (8 - 3 - lmul) >= sew
*/
if (vlmul == 4 ||
- cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) {
+ ((cpu->cfg.vlenb << 3) >> (8 - vlmul)) < sew) {
vill = true;
}
}
--
2.34.1
next reply other threads:[~2024-03-06 16:11 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-06 16:10 Max Chou [this message]
2024-03-06 17:17 ` [PATCH] target/riscv/vector_helper.c: Avoid shifting negative in fractional LMUL checking Daniel Henrique Barboza
2024-03-07 14:54 ` Max Chou
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