From: Andrew Jones <ajones@ventanamicro.com>
To: Himanshu Chauhan <hchauhan@ventanamicro.com>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v6 3/3] target/riscv: Enable sdtrig for Ventana's Veyron CPUs
Date: Thu, 14 Mar 2024 18:13:19 +0100 [thread overview]
Message-ID: <20240314-00815f922c7320ceca28398b@orel> (raw)
In-Reply-To: <20240314113510.477862-4-hchauhan@ventanamicro.com>
On Thu, Mar 14, 2024 at 05:05:10PM +0530, Himanshu Chauhan wrote:
> Ventana's Veyron CPUs support sdtrig ISA extension. By default, enable
> the sdtrig extension and disable the debug property for these CPUs.
The commit message needs to be updated to remove the 'and disable the
debug property'.
>
> Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
> ---
> target/riscv/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 66c91fffd6..3c7ad1c903 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -569,6 +569,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
> cpu->cfg.cbom_blocksize = 64;
> cpu->cfg.cboz_blocksize = 64;
> cpu->cfg.ext_zicboz = true;
> + cpu->cfg.ext_sdtrig = true;
> cpu->cfg.ext_smaia = true;
> cpu->cfg.ext_ssaia = true;
> cpu->cfg.ext_sscofpmf = true;
> --
> 2.34.1
>
Thanks,
drew
prev parent reply other threads:[~2024-03-14 17:13 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-14 11:35 [PATCH v6 0/3] Introduce sdtrig ISA extension Himanshu Chauhan
2024-03-14 11:35 ` [PATCH v6 1/3] target/riscv: Enable mcontrol6 triggers only when sdtrig is selected Himanshu Chauhan
2024-03-14 17:07 ` Andrew Jones
2024-03-14 11:35 ` [PATCH v6 2/3] target/riscv: Expose sdtrig ISA extension Himanshu Chauhan
2024-03-14 17:12 ` Andrew Jones
2024-03-14 11:35 ` [PATCH v6 3/3] target/riscv: Enable sdtrig for Ventana's Veyron CPUs Himanshu Chauhan
2024-03-14 17:13 ` Andrew Jones [this message]
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