From: Alistair Francis <alistair23@gmail.com>
To: qemu-riscv@nongnu.org, liwei1518@gmail.com,
zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
fabian.thomas@cispa.de, Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH] target/riscv: rvzicbo: Fixup CBO extension register calculation
Date: Tue, 14 May 2024 12:39:10 +1000 [thread overview]
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com> (raw)
When running the instruction
```
cbo.flush 0(x0)
```
QEMU would segfault.
The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
allocated.
In order to fix this let's use the existing get_address()
helper. This also has the benefit of performing pointer mask
calculations on the address specified in rs1.
The pointer masking specificiation specifically states:
"""
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
"""
So this is the correct behaviour and we previously have been incorrectly
not masking the address.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
---
target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index d5d7095903..15711c3140 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -31,27 +31,35 @@
static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
{
REQUIRE_ZICBOM(ctx);
- gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+ TCGv src = get_address(ctx, a->rs1, 0);
+
+ gen_helper_cbo_clean_flush(tcg_env, src);
return true;
}
static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
{
REQUIRE_ZICBOM(ctx);
- gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+ TCGv src = get_address(ctx, a->rs1, 0);
+
+ gen_helper_cbo_clean_flush(tcg_env, src);
return true;
}
static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
{
REQUIRE_ZICBOM(ctx);
- gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
+ TCGv src = get_address(ctx, a->rs1, 0);
+
+ gen_helper_cbo_inval(tcg_env, src);
return true;
}
static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
{
REQUIRE_ZICBOZ(ctx);
- gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
+ TCGv src = get_address(ctx, a->rs1, 0);
+
+ gen_helper_cbo_zero(tcg_env, src);
return true;
}
--
2.45.0
next reply other threads:[~2024-05-14 2:39 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-14 2:39 Alistair Francis [this message]
2024-05-14 7:09 ` [PATCH] target/riscv: rvzicbo: Fixup CBO extension register calculation Richard Henderson
2024-05-14 9:10 ` Daniel Henrique Barboza
2024-05-16 5:09 ` Alistair Francis
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