From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: SiHuaN <liyongtai@iscas.ac.cn>, qemu-devel@nongnu.org
Cc: "demin.han" <demin.han@starfivetech.com>,
qemu-riscv <qemu-riscv@nongnu.org>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: Re: [PATCH] Fix unexpected Illegal instruction error on RISC-V.
Date: Fri, 1 Mar 2024 16:51:03 +0100 [thread overview]
Message-ID: <4ed4b35a-659b-42d2-a0d9-9e7340b732f6@linaro.org> (raw)
In-Reply-To: <20240301145545.333810-2-liyongtai@iscas.ac.cn>
Hi SiHuaN,
On 1/3/24 15:55, SiHuaN wrote:
> Avoid right-shifting by a negative number of bits when lmul is 8.
FYI Demin posted a similar patch, see:
https://lore.kernel.org/qemu-devel/20240225174114.5298-1-demin.han@starfivetech.com/
> Signed-off-by: SiHuaN <liyongtai@iscas.ac.cn>
> ---
> target/riscv/vector_helper.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 84cec73eb2..f0158ea237 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -53,10 +53,11 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> * VLEN * LMUL >= SEW
> * VLEN >> (8 - lmul) >= sew
> * (vlenb << 3) >> (8 - lmul) >= sew
> + * Considering that lmul may be 8, the following form cannot be used.
> * vlenb >> (8 - 3 - lmul) >= sew
> */
> if (vlmul == 4 ||
> - cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) {
> + (cpu->cfg.vlenb << 3) >> (8 - vlmul) < sew) {
> vill = true;
> }
> }
next parent reply other threads:[~2024-03-01 15:51 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20240301145545.333810-2-liyongtai@iscas.ac.cn>
2024-03-01 15:51 ` Philippe Mathieu-Daudé [this message]
2024-03-01 16:15 ` Re: [PATCH] Fix unexpected Illegal instruction error on RISC-V 李永泰
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