messages from 2021-03-19 14:37:12 to 2021-04-09 07:49:53 UTC [more...]
[RFC PATCH 00/11] RISC-V: support clic v0.9 specification
2021-04-09 7:48 UTC (12+ messages)
` [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus
` [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode
` [RFC PATCH 03/11] hw/intc: Add CLIC device
` [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode
` [RFC PATCH 05/11] target/riscv: Update CSR xip "
` [RFC PATCH 06/11] target/riscv: Update CSR xtvec "
` [RFC PATCH 07/11] target/riscv: Update CSR xtvt "
` [RFC PATCH 08/11] target/riscv: Update CSR xnxti "
` [RFC PATCH 09/11] target/riscv: Update CSR mclicbase "
` [RFC PATCH 10/11] target/riscv: Update interrupt handling "
` [RFC PATCH 11/11] target/riscv: Update interrupt return "
[PATCH v1 0/8] RISC-V: Add support for ePMP v0.9.1
2021-04-09 4:24 UTC (17+ messages)
` [PATCH v1 1/8] target/riscv: Fix the PMP is locked check when using TOR
` [PATCH v1 2/8] target/riscv: Define ePMP mseccfg
` [PATCH v1 3/8] target/riscv: Add the ePMP feature
` [PATCH v1 4/8] target/riscv: Add ePMP CSR access functions
` [PATCH v1 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
` [PATCH v1 6/8] target/riscv: Add a config option for ePMP
` [PATCH v1 7/8] target/riscv/pmp: Remove outdated comment
` [PATCH v1 8/8] target/riscv: Add ePMP support for the Ibex CPU
[PATCH v1 0/8] RISC-V: Steps towards running 32-bit guests on
2021-04-08 18:51 UTC (20+ messages)
` [PATCH v1 1/8] target/riscv: Remove the hardcoded RVXLEN macro
` [PATCH v1 2/8] target/riscv: Remove the hardcoded SSTATUS_SD macro
` [PATCH v1 3/8] target/riscv: Remove the hardcoded HGATP_MODE macro
` [PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro
` [PATCH v1 5/8] target/riscv: Remove the hardcoded SATP_MODE macro
` [PATCH v1 6/8] target/riscv: Remove the unused HSTATUS_WPRI macro
` [PATCH v1 7/8] target/riscv: Remove an unused CASE_OP_32_64 macro
` [PATCH v1 8/8] target/riscv: Include RV32 instructions in RV64 build
[ RFC 0/6] Improve PMU support
2021-04-07 17:34 UTC (11+ messages)
` [ RFC 1/6] target/riscv: Remove privilege v1.9 specific CSR related code
` [ RFC 2/6] target/riscv: Implement mcountinhibit CSR
` [ RFC 3/6] target/riscv: Support mcycle/minstret write operation
` [ RFC 4/6] target/riscv: Add support for hpmcounters/hpmevents
` [ RFC 5/6] hw/riscv: virt: Add PMU device tree node to support SBI PMU extension
` [ RFC 6/6] hw/riscv: virt: DEBUG PATCH to test PMU
[PATCH] riscv: don't look at SUM when accessing memory from a debugger context
2021-04-07 14:50 UTC (3+ messages)
[PATCH v1 1/1] hw/riscv: Enalbe VIRTIO_VGA for RISC-V virt machine
2021-04-07 14:26 UTC (3+ messages)
[PATCH v1 1/1] hw/opentitan: Update the interrupt layout
2021-04-07 14:25 UTC (3+ messages)
[PATCH v1 1/1] MAINTAINERS: Update the RISC-V CPU Maintainers
2021-04-07 14:23 UTC (5+ messages)
[PATCH v2 0/5] RISC-V: Convert the CSR access functions to use
2021-04-07 13:55 UTC (16+ messages)
` [PATCH v2 1/5] target/riscv: Convert the RISC-V exceptions to an enum
` [PATCH v2 2/5] target/riscv: Use the RISCVException enum for CSR predicates
` [PATCH v2 3/5] target/riscv: Fix 32-bit HS mode access permissions
` [PATCH v2 4/5] target/riscv: Use the RISCVException enum for CSR operations
` [PATCH v2 5/5] target/riscv: Use RISCVException enum for CSR access
[PATCH v1 0/2] Add the SiFive PWM device
2021-04-07 13:54 UTC (5+ messages)
` [PATCH v1 1/2] sifive_u_pwm: Initial commit
` [PATCH v1 2/2] sifive_u: Connect the SiFive PWM device
Handling Timer Interrupts in Supervisor Mode (machine virt)
2021-04-05 17:01 UTC (2+ messages)
[PATCH v3 0/4] Add support for Shakti SoC from IIT-M
2021-04-04 11:43 UTC (12+ messages)
` [PATCH v3 1/4] target/riscv: Add Shakti C class CPU
` [PATCH v3 2/4] riscv: Add initial support for Shakti C machine
` [PATCH v3 3/4] hw/char: Add Shakti UART emulation
` [PATCH v3 4/4] hw/riscv: Connect Shakti UART to Shakti platform
[PATCH v2 0/4] Add support for Shakti SoC from IIT-M
2021-04-01 17:44 UTC (12+ messages)
` [PATCH v2 1/4] target/riscv: Add Shakti C class CPU
` [PATCH v2 2/4] riscv: Add initial support for Shakti C machine
` [PATCH v2 3/4] hw/char: Add Shakti UART emulation
` [PATCH v2 4/4] hw/riscv: Connect Shakti UART to Shakti platform
[RFC v2 0/4] target/riscv: add RNMI support
2021-04-01 9:36 UTC (6+ messages)
` [RFC v2 1/4] target/riscv: add RNMI cpu feature
` [RFC v2 2/4] target/riscv: add RNMI CSRs
` [RFC v2 3/4] target/riscv: handle RNMI interrupt and exception
` [RFC v2 4/4] target/riscv: add RNMI mnret instruction
[PATCH 1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
2021-03-31 16:07 UTC (17+ messages)
` [PATCH 2/8] hw/riscv: virt: "
` [PATCH 3/8] hw/riscv: Support the official CLINT DT bindings
` [PATCH 4/8] hw/riscv: Support the official PLIC "
` [PATCH 5/8] docs/system/riscv: Correct the indentation level of supported devices
` [PATCH 6/8] docs/system/riscv: sifive_u: Document '-dtb' usage
` [PATCH 7/8] hw/riscv: Use macros for BIOS image names
` [PATCH 8/8] hw/riscv: microchip_pfsoc: Support direct kernel boot
[PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64
2021-03-31 15:51 UTC (4+ messages)
` [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines
[PATCH] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
2021-03-31 15:26 UTC (4+ messages)
[PATCH V4] target/riscv: Align the data type of reset vector address
2021-03-30 18:29 UTC (2+ messages)
[PATCH V5] target/riscv: Align the data type of reset vector address
2021-03-30 16:30 UTC (3+ messages)
[PATCH V3] target/riscv: Align the data type of reset vector address
2021-03-28 0:46 UTC (6+ messages)
[PATCH 1/2] hw/riscv: sifive_u: Allow passing custom DTB
2021-03-26 13:29 UTC (3+ messages)
[PATCH v2 for-6.0?] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
2021-03-25 18:14 UTC (4+ messages)
[PATCH V2] target/riscv: Align the data type of reset vector address
2021-03-25 9:28 UTC (2+ messages)
[PATCH] target/riscv: Align the data type of reset vector address
2021-03-25 3:59 UTC (5+ messages)
[RFC PATCH 09/13] blobs: Only install firmware blobs if riscv system targets are built
2021-03-23 21:28 UTC (2+ messages)
[PATCH] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
2021-03-23 10:54 UTC (4+ messages)
[PATCH v2] target/riscv: Prevent lost illegal instruction exceptions
2021-03-22 21:57 UTC (3+ messages)
[PATCH 1/2] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
2021-03-22 20:34 UTC (5+ messages)
` [PATCH 2/2] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
[PATCH v2] target/riscv: Add proper two-stage lookup exception detection
2021-03-22 14:30 UTC (3+ messages)
[PATCH] hw/riscv: Drop the unused fdt pointer
2021-03-22 14:28 UTC (2+ messages)
[RFC 0/1] target/riscv: add RNMI support
2021-03-22 2:04 UTC (6+ messages)
` [RFC 1/1] target/riscv: add support of RNMI
[PATCH 0/3] Add support for Shakti SoC from IIT-M
2021-03-20 9:46 UTC (10+ messages)
` [PATCH 1/3] riscv: Add initial support for Shakti C class
` [PATCH 2/3] hw/char: Add Shakti UART emulation
` [PATCH 3/3] hw/riscv: Connect Shakti UART to Shakti platform
[PATCH] target/riscv: Prevent lost illegal instruction exceptions
2021-03-19 15:22 UTC (2+ messages)
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