messages from 2021-04-01 18:15:45 to 2021-04-20 00:57:51 UTC [more...]
[RFC PATCH 00/11] RISC-V: support clic v0.9 specification
2021-04-20 0:57 UTC (17+ messages)
` [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus
` [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode
` [RFC PATCH 03/11] hw/intc: Add CLIC device
` [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode
` [RFC PATCH 05/11] target/riscv: Update CSR xip "
` [RFC PATCH 06/11] target/riscv: Update CSR xtvec "
` [RFC PATCH 07/11] target/riscv: Update CSR xtvt "
` [RFC PATCH 08/11] target/riscv: Update CSR xnxti "
` [RFC PATCH 09/11] target/riscv: Update CSR mclicbase "
` [RFC PATCH 10/11] target/riscv: Update interrupt handling "
` [RFC PATCH 11/11] target/riscv: Update interrupt return "
[PATCH v4 0/8] RISC-V: Add support for ePMP v0.9.1
2021-04-19 23:13 UTC (11+ messages)
` [PATCH v4 1/8] target/riscv: Fix the PMP is locked check when using TOR
` [PATCH v4 2/8] target/riscv: Define ePMP mseccfg
` [PATCH v4 3/8] target/riscv: Add the ePMP feature
` [PATCH v4 4/8] target/riscv: Add ePMP CSR access functions
` [PATCH v4 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
` [PATCH v4 6/8] target/riscv: Add a config option for ePMP
` [PATCH v4 7/8] target/riscv/pmp: Remove outdated comment
` [PATCH v4 8/8] target/riscv: Add ePMP support for the Ibex CPU
[PATCH] hw/riscv: Fix OT IBEX reset vector
2021-04-19 21:36 UTC (2+ messages)
[PATCH] target/riscv: fix vrgather macro index variable type bug
2021-04-19 15:30 UTC (2+ messages)
[PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
2021-04-19 15:28 UTC (2+ messages)
[PATCH v2 for-6.0?] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
2021-04-19 13:42 UTC (3+ messages)
[PATCH] target/riscv: fix vssub.vv saturation bug
2021-04-19 8:49 UTC (4+ messages)
[PATCH] target/riscv: fix wfi exception behavior
2021-04-16 11:34 UTC (3+ messages)
[PATCH] docs: Add documentation for shakti_c machine
2021-04-15 22:33 UTC (3+ messages)
(no subject)
2021-04-15 22:27 UTC (3+ messages)
`
[PATCH 00/38] target/riscv: support packed extension v0.9.2
2021-04-15 5:50 UTC (4+ messages)
[PATCH v3 0/8] RISC-V: Add support for ePMP v0.9.1
2021-04-15 4:17 UTC (11+ messages)
` [PATCH v3 1/8] target/riscv: Fix the PMP is locked check when using TOR
` [PATCH v3 2/8] target/riscv: Define ePMP mseccfg
` [PATCH v3 3/8] target/riscv: Add the ePMP feature
` [PATCH v3 4/8] target/riscv: Add ePMP CSR access functions
` [PATCH v3 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
` [PATCH v3 6/8] target/riscv: Add a config option for ePMP
` [PATCH v3 7/8] target/riscv/pmp: Remove outdated comment
` [PATCH v3 8/8] target/riscv: Add ePMP support for the Ibex CPU
[PATCH RFC v5 00/12] Add riscv kvm accel support
2021-04-14 22:50 UTC (19+ messages)
` [PATCH RFC v5 01/12] linux-header: Update linux/kvm.h
` [PATCH RFC v5 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
` [PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu
` [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers
` [PATCH RFC v5 05/12] target/riscv: Implement kvm_arch_put_registers
` [PATCH RFC v5 06/12] target/riscv: Support start kernel directly by KVM
` [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
` [PATCH RFC v5 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
` [PATCH RFC v5 09/12] target/riscv: Add host cpu type
` [PATCH RFC v5 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
` [PATCH RFC v5 11/12] target/riscv: Implement virtual time adjusting with vm state changing
` [PATCH RFC v5 12/12] target/riscv: Support virtual time context synchronization
[PATCH v2 0/9] RISC-V: Steps towards running 32-bit guests on
2021-04-14 8:00 UTC (20+ messages)
` [PATCH v2 1/9] target/riscv: Remove the hardcoded RVXLEN macro
` [PATCH v2 2/9] target/riscv: Remove the hardcoded SSTATUS_SD macro
` [PATCH v2 3/9] target/riscv: Remove the hardcoded HGATP_MODE macro
` [PATCH v2 4/9] target/riscv: Remove the hardcoded MSTATUS_SD macro
` [PATCH v2 5/9] target/riscv: Remove the hardcoded SATP_MODE macro
` [PATCH v2 6/9] target/riscv: Remove the unused HSTATUS_WPRI macro
` [PATCH v2 7/9] target/riscv: Remove an unused CASE_OP_32_64 macro
` [PATCH v2 8/9] target/riscv: Consolidate RV32/64 32-bit instructions
` [PATCH v2 9/9] target/riscv: Consolidate RV32/64 16-bit instructions
[PATCH] target/riscv: fix exception index on instruction access fault
2021-04-14 3:42 UTC (2+ messages)
Fix exception index on instruction access fault
2021-04-13 16:20 UTC
[PATCH v1 0/8] RISC-V: Steps towards running 32-bit guests on
2021-04-12 9:10 UTC (24+ messages)
` [PATCH v1 1/8] target/riscv: Remove the hardcoded RVXLEN macro
` [PATCH v1 2/8] target/riscv: Remove the hardcoded SSTATUS_SD macro
` [PATCH v1 3/8] target/riscv: Remove the hardcoded HGATP_MODE macro
` [PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro
` [PATCH v1 5/8] target/riscv: Remove the hardcoded SATP_MODE macro
` [PATCH v1 6/8] target/riscv: Remove the unused HSTATUS_WPRI macro
` [PATCH v1 7/8] target/riscv: Remove an unused CASE_OP_32_64 macro
` [PATCH v1 8/8] target/riscv: Include RV32 instructions in RV64 build
[PATCH v1 0/8] RISC-V: Add support for ePMP v0.9.1
2021-04-11 23:03 UTC (18+ messages)
` [PATCH v1 1/8] target/riscv: Fix the PMP is locked check when using TOR
` [PATCH v1 2/8] target/riscv: Define ePMP mseccfg
` [PATCH v1 3/8] target/riscv: Add the ePMP feature
` [PATCH v1 4/8] target/riscv: Add ePMP CSR access functions
` [PATCH v1 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
` [PATCH v1 6/8] target/riscv: Add a config option for ePMP
` [PATCH v1 7/8] target/riscv/pmp: Remove outdated comment
` [PATCH v1 8/8] target/riscv: Add ePMP support for the Ibex CPU
[PATCH v2 0/8] RISC-V: Add support for ePMP v0.9.1
2021-04-11 4:06 UTC (11+ messages)
` [PATCH v2 1/8] target/riscv: Fix the PMP is locked check when using TOR
` [PATCH v2 2/8] target/riscv: Define ePMP mseccfg
` [PATCH v2 3/8] target/riscv: Add the ePMP feature
` [PATCH v2 4/8] target/riscv: Add ePMP CSR access functions
` [PATCH v2 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
` [PATCH v2 6/8] target/riscv: Add a config option for ePMP
` [PATCH v2 7/8] target/riscv/pmp: Remove outdated comment
` [PATCH v2 8/8] target/riscv: Add ePMP support for the Ibex CPU
medeleg[11] should be hardwired to zero?
2021-04-09 20:15 UTC
[ RFC 0/6] Improve PMU support
2021-04-07 17:34 UTC (5+ messages)
` [ RFC 3/6] target/riscv: Support mcycle/minstret write operation
` [ RFC 4/6] target/riscv: Add support for hpmcounters/hpmevents
[PATCH] riscv: don't look at SUM when accessing memory from a debugger context
2021-04-07 14:50 UTC (3+ messages)
[PATCH v1 1/1] hw/riscv: Enalbe VIRTIO_VGA for RISC-V virt machine
2021-04-07 14:26 UTC (3+ messages)
[PATCH v1 1/1] hw/opentitan: Update the interrupt layout
2021-04-07 14:25 UTC (3+ messages)
[PATCH v1 1/1] MAINTAINERS: Update the RISC-V CPU Maintainers
2021-04-07 14:23 UTC (5+ messages)
[PATCH v2 0/5] RISC-V: Convert the CSR access functions to use
2021-04-07 13:55 UTC (16+ messages)
` [PATCH v2 1/5] target/riscv: Convert the RISC-V exceptions to an enum
` [PATCH v2 2/5] target/riscv: Use the RISCVException enum for CSR predicates
` [PATCH v2 3/5] target/riscv: Fix 32-bit HS mode access permissions
` [PATCH v2 4/5] target/riscv: Use the RISCVException enum for CSR operations
` [PATCH v2 5/5] target/riscv: Use RISCVException enum for CSR access
[PATCH v1 0/2] Add the SiFive PWM device
2021-04-07 13:54 UTC (5+ messages)
` [PATCH v1 1/2] sifive_u_pwm: Initial commit
` [PATCH v1 2/2] sifive_u: Connect the SiFive PWM device
Handling Timer Interrupts in Supervisor Mode (machine virt)
2021-04-05 17:01 UTC (2+ messages)
[PATCH v3 0/4] Add support for Shakti SoC from IIT-M
2021-04-04 11:43 UTC (12+ messages)
` [PATCH v3 1/4] target/riscv: Add Shakti C class CPU
` [PATCH v3 2/4] riscv: Add initial support for Shakti C machine
` [PATCH v3 3/4] hw/char: Add Shakti UART emulation
` [PATCH v3 4/4] hw/riscv: Connect Shakti UART to Shakti platform
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