messages from 2021-04-15 13:42:19 to 2021-05-04 16:33:31 UTC [more...]
[PATCH 0/2] QOMify Sifive UART model
2021-05-04 15:34 UTC (3+ messages)
` [PATCH 1/2] Consistent function names for sifive uart read and write function
` [PATCH 2/2] QOMify sifive_uart model
[PATCH v1 1/1] docs/system: Move the RISC-V -bios information to removed
2021-05-04 3:12 UTC (2+ messages)
[PATCH v2] target/riscv: fix VS interrupts forwarding to HS
2021-05-03 20:44 UTC
[PATCH v2 1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
2021-05-03 3:00 UTC (9+ messages)
` [PATCH v2 2/8] hw/riscv: virt: "
` [PATCH v2 3/8] hw/riscv: Support the official CLINT DT bindings
` [PATCH v2 4/8] hw/riscv: Support the official PLIC "
` [PATCH v2 5/8] docs/system/riscv: Correct the indentation level of supported devices
` [PATCH v2 6/8] docs/system/riscv: sifive_u: Document '-dtb' usage
` [PATCH v2 7/8] hw/riscv: Use macros for BIOS image names
` [PATCH v2 8/8] hw/riscv: microchip_pfsoc: Support direct kernel boot
[PATCH] docs/system: riscv: Include shakti_c machine documentation
2021-04-30 7:05 UTC
[PATCH RFC v5 00/12] Add riscv kvm accel support
2021-04-30 4:53 UTC (3+ messages)
` [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
[PATCH 0/7] hw/nvram/fw_cfg: Do not build device if not needed (Spring cleanup)
2021-04-28 18:50 UTC (18+ messages)
` [PATCH 1/7] stubs: Restrict fw_cfg stubs to sysemu
` [PATCH 2/7] hw/nvram: Rename FW_CFG_MIPS as generic FW_CFG Kconfig symbol
` [PATCH 3/7] hw/nvram: Declare FW_CFG_DMA Kconfig symbol in hw/nvram/
` [PATCH 4/7] hw/acpi/vmgenid: Make ACPI_VMGENID depends on FW_CFG Kconfig
` [PATCH 5/7] hw: Have machines Kconfig-select FW_CFG
` [PATCH 6/7] hw/{arm,hppa,riscv}: Add fw_cfg arch-specific stub
` [PATCH 7/7] hw/nvram: Do not build FW_CFG if not required
[PATCH] target/riscv: Dump CSR mscratch/sscratch/satp
2021-04-28 12:25 UTC
[PATCH RESEND v8 0/6] RISC-V Pointer Masking implementation
2021-04-28 4:18 UTC (7+ messages)
` [PATCH v8 1/6] [RISCV_PM] Add J-extension into RISC-V
` [PATCH RESEND v8 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
` [PATCH v8 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs
` [PATCH v8 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
` [PATCH v8 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
` [PATCH v8 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
[PATCH RESEND v8 0/6] RISC-V Pointer Masking implementation
2021-04-28 4:07 UTC
[PATCH RESEND v8 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
2021-04-28 3:55 UTC
[PATCH v8 0/6] RISC-V Pointer Masking implementation
2021-04-27 22:18 UTC (8+ messages)
` [PATCH v8 1/6] [RISCV_PM] Add J-extension into RISC-V
` [PATCH v8 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
` [PATCH v8 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs
` [PATCH v8 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
` [PATCH v8 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
` [PATCH v8 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
[PATCH v5 00/17] support subsets of bitmanip extension
2021-04-27 7:13 UTC (25+ messages)
` [PATCH v5 01/17] target/riscv: reformat @sh format encoding for B-extension
` [PATCH v5 02/17] target/riscv: rvb: count leading/trailing zeros
` [PATCH v5 03/17] target/riscv: rvb: count bits set
` [PATCH v5 04/17] target/riscv: rvb: logic-with-negate
` [PATCH v5 05/17] target/riscv: rvb: pack two words into one register
` [PATCH v5 06/17] target/riscv: rvb: min/max instructions
` [PATCH v5 07/17] target/riscv: rvb: sign-extend instructions
` [PATCH v5 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions
` [PATCH v5 09/17] target/riscv: rvb: single-bit instructions
` [PATCH v5 10/17] target/riscv: rvb: shift ones
` [PATCH v5 11/17] target/riscv: rvb: rotate (left/right)
` [PATCH v5 12/17] target/riscv: rvb: generalized reverse
` [PATCH v5 13/17] target/riscv: rvb: generalized or-combine
` [PATCH v5 14/17] target/riscv: rvb: address calculation
` [PATCH v5 15/17] target/riscv: rvb: add/shift with prefix zero-extend
` [PATCH v5 16/17] target/riscv: rvb: support and turn on B-extension from command line
` [PATCH v5 17/17] target/riscv: rvb: add b-ext version cpu option
[PATCH v2] target/riscv: fix wfi exception behavior
2021-04-27 6:09 UTC (2+ messages)
[PATCH v6 00/18] cpu: Introduce SysemuCPUOps structure
2021-04-26 16:50 UTC (25+ messages)
` [PATCH v6 01/18] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
` [PATCH v6 02/18] cpu: Introduce cpu_virtio_is_big_endian()
` [PATCH v6 03/18] cpu: Directly use cpu_write_elf*() fallback handlers in place
` [PATCH v6 04/18] cpu: Directly use get_paging_enabled() "
` [PATCH v6 05/18] cpu: Directly use get_memory_mapping() "
` [PATCH v6 06/18] cpu: Assert DeviceClass::vmsd is NULL on user emulation
` [PATCH v6 07/18] cpu: Rename CPUClass vmsd -> legacy_vmsd
` [PATCH v6 08/18] cpu/{avr, lm32, moxie}: Set DeviceClass vmsd field (not CPUClass one)
` [PATCH v6 09/18] cpu: Introduce SysemuCPUOps structure
` [PATCH v6 10/18] cpu: Move CPUClass::vmsd to SysemuCPUOps
` [PATCH v6 11/18] cpu: Move CPUClass::virtio_is_big_endian "
` [PATCH v6 12/18] cpu: Move CPUClass::get_crash_info "
` [PATCH v6 13/18] cpu: Move CPUClass::write_elf* "
` [PATCH v6 14/18] cpu: Move CPUClass::asidx_from_attrs "
` [PATCH v6 15/18] cpu: Move CPUClass::get_phys_page_debug "
` [PATCH v6 16/18] cpu: Move CPUClass::get_memory_mapping "
` [PATCH v6 17/18] cpu: Move CPUClass::get_paging_enabled "
` [PATCH v6 18/18] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
[PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on
2021-04-26 5:33 UTC (18+ messages)
` [PATCH v3 01/10] target/riscv: Remove the hardcoded RVXLEN macro
` [PATCH v3 02/10] target/riscv: Remove the hardcoded SSTATUS_SD macro
` [PATCH v3 03/10] target/riscv: Remove the hardcoded HGATP_MODE macro
` [PATCH v3 04/10] target/riscv: Remove the hardcoded MSTATUS_SD macro
` [PATCH v3 05/10] target/riscv: Remove the hardcoded SATP_MODE macro
` [PATCH v3 06/10] target/riscv: Remove the unused HSTATUS_WPRI macro
` [PATCH v3 07/10] target/riscv: Remove an unused CASE_OP_32_64 macro
` [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions
` [PATCH v3 09/10] target/riscv: Consolidate RV32/64 16-bit instructions
` [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment
[PATCH v3 00/27] cpu: Introduce SysemuCPUOps structure, remove watchpoints from usermode
2021-04-22 16:05 UTC (9+ messages)
` [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
[PATCH v5 00/15] cpu: Introduce SysemuCPUOps structure
2021-04-22 11:04 UTC (17+ messages)
` [PATCH v5 01/15] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
` [PATCH v5 02/15] cpu: Introduce cpu_virtio_is_big_endian()
` [PATCH v5 03/15] cpu: Directly use cpu_write_elf*() fallback handlers in place
` [PATCH v5 04/15] cpu: Directly use get_paging_enabled() "
` [PATCH v5 05/15] cpu: Directly use get_memory_mapping() "
` [PATCH v5 06/15] cpu: Introduce SysemuCPUOps structure
` [PATCH v5 07/15] cpu: Move CPUClass::vmsd to SysemuCPUOps
` [PATCH v5 08/15] cpu: Move CPUClass::virtio_is_big_endian "
` [PATCH v5 09/15] cpu: Move CPUClass::get_crash_info "
` [PATCH v5 10/15] cpu: Move CPUClass::write_elf* "
` [PATCH v5 11/15] cpu: Move CPUClass::asidx_from_attrs "
` [PATCH v5 12/15] cpu: Move CPUClass::get_phys_page_debug "
` [PATCH v5 13/15] cpu: Move CPUClass::get_memory_mapping "
` [PATCH v5 14/15] cpu: Move CPUClass::get_paging_enabled "
` [PATCH v5 15/15] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
[PATCH v2 0/9] RISC-V: Steps towards running 32-bit guests on
2021-04-22 2:01 UTC (4+ messages)
` [PATCH v2 8/9] target/riscv: Consolidate RV32/64 32-bit instructions
[PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
2021-04-22 1:42 UTC (5+ messages)
[PATCH] target/riscv: fix a typo with interrupt names
2021-04-22 0:24 UTC (2+ messages)
[RFC PATCH 00/11] RISC-V: support clic v0.9 specification
2021-04-22 0:21 UTC (13+ messages)
` [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus
` [RFC PATCH 03/11] hw/intc: Add CLIC device
[RFC] target/riscv: generated RISCV isa string and subset naming convention
2021-04-21 14:18 UTC
[PATCH v2 for-6.0?] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
2021-04-20 12:39 UTC (8+ messages)
[PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
2021-04-20 1:18 UTC (3+ messages)
[PATCH v4 0/8] RISC-V: Add support for ePMP v0.9.1
2021-04-19 23:13 UTC (11+ messages)
` [PATCH v4 1/8] target/riscv: Fix the PMP is locked check when using TOR
` [PATCH v4 2/8] target/riscv: Define ePMP mseccfg
` [PATCH v4 3/8] target/riscv: Add the ePMP feature
` [PATCH v4 4/8] target/riscv: Add ePMP CSR access functions
` [PATCH v4 5/8] target/riscv: Implementation of enhanced PMP (ePMP)
` [PATCH v4 6/8] target/riscv: Add a config option for ePMP
` [PATCH v4 7/8] target/riscv/pmp: Remove outdated comment
` [PATCH v4 8/8] target/riscv: Add ePMP support for the Ibex CPU
[PATCH] hw/riscv: Fix OT IBEX reset vector
2021-04-19 21:36 UTC (2+ messages)
[PATCH] target/riscv: fix vrgather macro index variable type bug
2021-04-19 15:30 UTC (2+ messages)
[PATCH] target/riscv: fix vssub.vv saturation bug
2021-04-19 8:49 UTC (4+ messages)
[PATCH] target/riscv: fix wfi exception behavior
2021-04-16 11:34 UTC (3+ messages)
[PATCH] docs: Add documentation for shakti_c machine
2021-04-15 22:33 UTC (2+ messages)
(no subject)
2021-04-15 22:27 UTC (3+ messages)
`
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