messages from 2021-06-10 07:59:25 to 2021-06-28 08:45:19 UTC [more...]
[RFC PATCH 00/11] RISC-V: support clic v0.9 specification
2021-06-28 8:43 UTC (46+ messages)
` [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode
` [RFC PATCH 03/11] hw/intc: Add CLIC device
` [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode
` [RFC PATCH 05/11] target/riscv: Update CSR xip "
` [RFC PATCH 06/11] target/riscv: Update CSR xtvec "
` [RFC PATCH 07/11] target/riscv: Update CSR xtvt "
` [RFC PATCH 08/11] target/riscv: Update CSR xnxti "
` [RFC PATCH 09/11] target/riscv: Update CSR mclicbase "
` [RFC PATCH 10/11] target/riscv: Update interrupt handling "
` [RFC PATCH 11/11] target/riscv: Update interrupt return "
[PATCH] target/riscv: pmp: Fix some typos
2021-06-28 0:21 UTC (3+ messages)
[PATCH 1/2] docs/system: riscv: Fix CLINT name in the sifive_u doc
2021-06-28 0:21 UTC (3+ messages)
` [PATCH 2/2] docs/system: riscv: Add documentation for virt machine
[PATCH v2] target/riscv: csr: Remove redundant check in fp csr read/write routines
2021-06-27 12:06 UTC
[PATCH] target/riscv: hardwire bits in hideleg and hedeleg
2021-06-24 13:48 UTC (3+ messages)
[PATCH v3 00/37] target/riscv: support packed extension v0.9.4
2021-06-24 11:55 UTC (39+ messages)
` [PATCH v3 01/37] target/riscv: implementation-defined constant parameters
` [PATCH v3 02/37] target/riscv: Make the vector helper functions public
` [PATCH v3 03/37] target/riscv: 16-bit Addition & Subtraction Instructions
` [PATCH v3 04/37] target/riscv: 8-bit Addition & Subtraction Instruction
` [PATCH v3 05/37] target/riscv: SIMD 16-bit Shift Instructions
` [PATCH v3 06/37] target/riscv: SIMD 8-bit "
` [PATCH v3 07/37] target/riscv: SIMD 16-bit Compare Instructions
` [PATCH v3 08/37] target/riscv: SIMD 8-bit "
` [PATCH v3 09/37] target/riscv: SIMD 16-bit Multiply Instructions
` [PATCH v3 10/37] target/riscv: SIMD 8-bit "
` [PATCH v3 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions
` [PATCH v3 12/37] target/riscv: SIMD 8-bit "
` [PATCH v3 13/37] target/riscv: 8-bit Unpacking Instructions
` [PATCH v3 14/37] target/riscv: 16-bit Packing Instructions
` [PATCH v3 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions
` [PATCH v3 16/37] target/riscv: Signed MSW 32x16 "
` [PATCH v3 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
` [PATCH v3 18/37] target/riscv: Signed 16-bit Multiply 64-bit "
` [PATCH v3 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions
` [PATCH v3 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions
` [PATCH v3 21/37] target/riscv: 64-bit Add/Subtract Instructions
` [PATCH v3 22/37] target/riscv: 32-bit Multiply "
` [PATCH v3 23/37] target/riscv: Signed 16-bit Multiply with "
` [PATCH v3 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions
` [PATCH v3 25/37] target/riscv: Non-SIMD Q31 "
` [PATCH v3 26/37] target/riscv: 32-bit Computation Instructions
` [PATCH v3 27/37] target/riscv: Non-SIMD Miscellaneous Instructions
` [PATCH v3 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
` [PATCH v3 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions
` [PATCH v3 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
` [PATCH v3 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
` [PATCH v3 32/37] target/riscv: RV64 Only 32-bit "
` [PATCH v3 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions
` [PATCH v3 34/37] target/riscv: RV64 Only 32-bit Parallel "
` [PATCH v3 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
` [PATCH v3 36/37] target/riscv: RV64 Only 32-bit Packing Instructions
` [PATCH v3 37/37] target/riscv: configure and turn on packed extension from command line
[PATCH v2 00/37] target/riscv: support packed extension v0.9.4
2021-06-24 6:05 UTC (44+ messages)
` [PATCH v2 01/37] target/riscv: implementation-defined constant parameters
` [PATCH v2 02/37] target/riscv: Make the vector helper functions public
` [PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions
` [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction
` [PATCH v2 05/37] target/riscv: SIMD 16-bit Shift Instructions
` [PATCH v2 06/37] target/riscv: SIMD 8-bit "
` [PATCH v2 07/37] target/riscv: SIMD 16-bit Compare Instructions
` [PATCH v2 08/37] target/riscv: SIMD 8-bit "
` [PATCH v2 09/37] target/riscv: SIMD 16-bit Multiply Instructions
` [PATCH v2 10/37] target/riscv: SIMD 8-bit "
` [PATCH v2 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions
` [PATCH v2 12/37] target/riscv: SIMD 8-bit "
` [PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions
` [PATCH v2 14/37] target/riscv: 16-bit Packing Instructions
` [PATCH v2 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions
` [PATCH v2 16/37] target/riscv: Signed MSW 32x16 "
` [PATCH v2 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
` [PATCH v2 18/37] target/riscv: Signed 16-bit Multiply 64-bit "
` [PATCH v2 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions
` [PATCH v2 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions
` [PATCH v2 21/37] target/riscv: 64-bit Add/Subtract Instructions
` [PATCH v2 22/37] target/riscv: 32-bit Multiply "
` [PATCH v2 23/37] target/riscv: Signed 16-bit Multiply with "
` [PATCH v2 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions
` [PATCH v2 25/37] target/riscv: Non-SIMD Q31 "
` [PATCH v2 26/37] target/riscv: 32-bit Computation Instructions
` [PATCH v2 27/37] target/riscv: Non-SIMD Miscellaneous Instructions
` [PATCH v2 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
` [PATCH v2 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions
` [PATCH v2 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
` [PATCH v2 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
` [PATCH v2 32/37] target/riscv: RV64 Only 32-bit "
` [PATCH v2 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions
` [PATCH v2 34/37] target/riscv: RV64 Only 32-bit Parallel "
` [PATCH v2 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
` [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions
` [PATCH v2 37/37] target/riscv: configure and turn on packed extension from command line
[PATCH v3 0/3] OpenTitan: Add support for the RISC-V timer
2021-06-21 22:39 UTC (6+ messages)
` [PATCH v3 1/3] hw/char/ibex_uart: Make the register layout private
` [PATCH v3 2/3] hw/timer: Initial commit of Ibex Timer
` [PATCH v3 3/3] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
[PATCH 18/26] target/riscv: Use translator_use_goto_tb
2021-06-21 22:22 UTC (2+ messages)
[PATCH v1 1/5] meson: Introduce target-specific Kconfig
2021-06-21 15:21 UTC
[PATCH v16 93/99] meson: Introduce target-specific Kconfig
2021-06-18 16:31 UTC (3+ messages)
[PATCH v5 0/2] QOMify Sifive UART Model
2021-06-18 7:23 UTC (5+ messages)
` [PATCH v5 1/2] hw/char: Consistent function names for sifive_uart
` [PATCH v5 2/2] hw/char: QOMify sifive_uart
[PATCH v2 0/3] hw/riscv: OpenTitan: Add support for the RISC-V timer
2021-06-18 7:02 UTC (8+ messages)
` [PATCH v2 2/3] hw/timer: Initial commit of Ibex Timer
[PATCH v1 0/3] RISC-V ACLINT Support
2021-06-18 6:50 UTC (8+ messages)
` [PATCH v1 1/3] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
` [PATCH v1 2/3] hw/riscv: virt: Re-factor FDT generation
` [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine
[PATCH] target/riscv: gdbstub: Fix dynamic CSR XML generation
2021-06-18 6:39 UTC (3+ messages)
[PATCH 16/21] linux-user/riscv: Implement setup_sigtramp
2021-06-18 1:29 UTC (3+ messages)
[PATCH v4 0/2] QOMify Sifive UART Model
2021-06-16 9:15 UTC (6+ messages)
` [PATCH v4 1/2] hw/char: Consistent function names for sifive_uart
` [PATCH v4 2/2] hw/char: QOMify sifive_uart
[PATCH 0/4] AIA local interrupt CSR support
2021-06-15 12:48 UTC (17+ messages)
` [PATCH 1/4] target/riscv: Add defines for AIA local interrupt CSRs
` [PATCH 2/4] target/riscv: Add CPU feature for AIA CSRs
` [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs
` [PATCH 4/4] hw/riscv: virt: Use AIA INTC compatible string when available
[PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64
2021-06-15 10:42 UTC (5+ messages)
` [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines
[PATCH v3 0/2] QOMify Sifive UART Model
2021-06-15 8:16 UTC (7+ messages)
` [PATCH v3 1/2] hw/char: sifive_uart
` [PATCH v3 2/2] "
TCG op for 32 bit only cpu on qemu-riscv64
2021-06-11 2:33 UTC (5+ messages)
[RFC PATCH v3 0/2] Proposing custom CSR handling logic
2021-06-10 23:22 UTC (7+ messages)
` [RFC PATCH v3 1/2] Adding Andes AX25 CPU model
` [RFC PATCH v3 2/2] Adding preliminary custom/vendor CSR handling mechanism
[PATCH 0/2] target/riscv: fix hypervisor exceptions
2021-06-10 23:14 UTC (5+ messages)
` [PATCH 1/2] target/riscv: fix VS interrupts forwarding to HS
` [PATCH 2/2] target/riscv: remove force HS exception
[PATCH v1 1/1] target/riscv: Use target_ulong for the DisasContext misa
2021-06-10 23:02 UTC (2+ messages)
[PATCH v9 0/6] RISC-V Pointer Masking implementation
2021-06-10 22:46 UTC (3+ messages)
` [PATCH v9 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
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