messages from 2024-03-07 01:43:22 to 2024-03-14 06:16:22 UTC [more...]
[PATCH v2 1/1] target/riscv/kvm: fix timebase-frequency when using KVM acceleration
2024-03-14 6:15 UTC
[PATCH for-9.0 v14 0/8] riscv: set vstart_eq_zero on vector insns
2024-03-14 3:52 UTC (11+ messages)
` [PATCH for-9.0 v14 1/8] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
` [PATCH for-9.0 v14 2/8] trans_rvv.c.inc: set vstart = 0 in int scalar move insns
` [PATCH for-9.0 v14 3/8] target/riscv: always clear vstart in whole vec "
` [PATCH for-9.0 v14 4/8] target/riscv/vector_helpers: do early exit when vstart >= vl
` [PATCH for-9.0 v14 5/8] target/riscv: remove 'over' brconds from vector trans
` [PATCH for-9.0 v14 6/8] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
` [PATCH for-9.0 v14 7/8] target/riscv: enable 'vstart_eq_zero' in the end of insns
` [PATCH for-9.0 v14 8/8] target/riscv/vector_helper.c: optimize loops in ldst helpers
[PATCH for-9.0 v13 0/8] riscv: set vstart_eq_zero on vector insns
2024-03-13 21:39 UTC (11+ messages)
` [PATCH for-9.0 v13 1/8] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
` [PATCH for-9.0 v13 2/8] trans_rvv.c.inc: set vstart = 0 in int scalar move insns
` [PATCH for-9.0 v13 3/8] target/riscv/vector_helpers: do early exit when vstart >= vl
` [PATCH for-9.0 v13 4/8] target/riscv: always clear vstart in whole vec move insns
` [PATCH for-9.0 v13 5/8] target/riscv: remove 'over' brconds from vector trans
` [PATCH for-9.0 v13 6/8] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
` [PATCH for-9.0 v13 7/8] target/riscv: enable 'vstart_eq_zero' in the end of insns
` [PATCH for-9.0 v13 8/8] target/riscv/vector_helper.c: optimize loops in ldst helpers
[PATCH v3] target/riscv: Implement dynamic establishment of custom decoder
2024-03-13 20:32 UTC (3+ messages)
[PATCH for-9.0] target/riscv: do not enable all named features by default
2024-03-13 20:13 UTC (3+ messages)
[PATCH v5 0/3] Introduce sdtrig ISA extension
2024-03-13 19:15 UTC (7+ messages)
` [PATCH v5 1/3] target/riscv: Enable mcontrol6 triggers only when sdtrig is selected
` [PATCH v5 2/3] target/riscv: Expose sdtrig ISA extension
` [PATCH v5 3/3] target/riscv: Enable sdtrig for Ventana's Veyron CPUs
[PATCH v4 0/3] Introduce sdtrig ISA extension
2024-03-13 13:31 UTC (12+ messages)
` [PATCH v4 1/3] target/riscv: Enable mcontrol6 triggers only when sdtrig is selected
` [PATCH v4 2/3] target/riscv: Expose sdtrig ISA extension
` [PATCH v4 3/3] target/riscv: Enable sdtrig for Ventana's Veyron CPUs
[PATCH 1/1] target/riscv/kvm: fix timebase-frequency when using KVM acceleration
2024-03-13 10:24 UTC (3+ messages)
Weird behavior on RISC-V code running on QEMU
2024-03-13 9:24 UTC (2+ messages)
[PATCH v2] target/riscv: Implement dynamic establishment of custom decoder
2024-03-13 8:38 UTC (3+ messages)
[PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
2024-03-13 1:50 UTC
[PATCH] target/riscv: Raise exceptions on wrs.nto
2024-03-12 15:30 UTC (3+ messages)
[PATCH v2] target/riscv: Raise exceptions on wrs.nto
2024-03-12 15:29 UTC
[RFC v2 0/2] Add RISC-V Server Platform Reference Board
2024-03-12 13:52 UTC (3+ messages)
` [RFC v2 1/2] target/riscv: Add server platform reference cpu
` [RFC v2 2/2] hw/riscv: Add server platform reference machine
[RFC 0/2] Add RISC-V Server Platform Reference Board
2024-03-12 12:52 UTC (23+ messages)
` [RFC 1/2] hw/riscv: Add server platform reference machine
` [RISC-V][tech-server-platform] "
` [RISC-V][tech-server-soc] "
` [RFC 2/2] target/riscv: Add server platform reference cpu
` [RISC-V][tech-server-soc] "
` [RISC-V][tech-server-platform] "
[PATCH v3 00/29] hw, target: Prefer fast cpu_env() over slower CPU QOM cast macro
2024-03-12 11:24 UTC (7+ messages)
` [PATCH v3 01/29] bulk: Access existing variables initialized to &S->F when available
` [PATCH v3 14/29] target/i386: Prefer fast cpu_env() over slower CPU QOM cast macro
[PATCH] disas/riscv: Further correction to LUI disassembly
2024-03-12 11:09 UTC (11+ messages)
[PULL 09/34] target/riscv: add remaining named features
2024-03-12 9:26 UTC (2+ messages)
[PATCH v2] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
2024-03-12 2:36 UTC (3+ messages)
[PATCH v12 0/7] riscv: set vstart_eq_zero on vector insns
2024-03-12 1:58 UTC (9+ messages)
` [PATCH v12 1/7] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
` [PATCH v12 2/7] trans_rvv.c.inc: set vstart = 0 in int scalar move insns
` [PATCH v12 3/7] target/riscv/vector_helpers: do early exit when vstart >= vl
` [PATCH v12 4/7] target/riscv: remove 'over' brconds from vector trans
` [PATCH v12 5/7] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
` [PATCH v12 6/7] target/riscv: enable 'vstart_eq_zero' in the end of insns
` [PATCH v12 7/7] target/riscv/vector_helper.c: optimize loops in ldst helpers
[PATCH v11 0/7] riscv: set vstart_eq_zero on vector insns
2024-03-11 17:15 UTC (10+ messages)
` [PATCH v11 1/7] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
` [PATCH v11 2/7] trans_rvv.c.inc: set vstart = 0 in int scalar move insns
` [PATCH v11 3/7] target/riscv/vector_helpers: do early exit when vstart >= vl
` [PATCH v11 4/7] target/riscv: remove 'over' brconds from vector trans
` [PATCH v11 5/7] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
` [PATCH v11 6/7] target/riscv: enable 'vstart_eq_zero' in the end of insns
` [PATCH v11 7/7] target/riscv/vector_helper.c: optimize loops in ldst helpers
[PATCH v9 00/10] riscv: set vstart_eq_zero on mark_vs_dirty
2024-03-11 2:40 UTC (22+ messages)
` [PATCH v9 01/10] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
` [PATCH v9 02/10] target/riscv: handle vstart >= vl in vext_set_tail_elems_1s()
` [PATCH v9 03/10] target/riscv/vector_helper.c: do vstart=0 after updating tail
` [PATCH v9 04/10] target/riscv/vector_helper.c: update tail with vext_set_tail_elems_1s()
` [PATCH v9 05/10] target/riscv: use vext_set_tail_elems_1s() in vcrypto insns
` [PATCH v9 06/10] trans_rvv.c.inc: set vstart = 0 in int scalar move insns
` [PATCH v9 07/10] target/riscv: remove 'over' brconds from vector trans
` [PATCH v9 08/10] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
` [PATCH v9 09/10] target/riscv: Clear vstart_qe_zero flag
` [PATCH v9 10/10] target/riscv/vector_helper.c: optimize loops in ldst helpers
[PATCH v10 00/10] riscv: set vstart_eq_zero on mark_vs_dirty
2024-03-10 11:53 UTC (11+ messages)
` [PATCH v10 01/10] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
` [PATCH v10 02/10] target/riscv: handle vstart >= vl in vext_set_tail_elems_1s()
` [PATCH v10 03/10] target/riscv/vector_helper.c: do vstart=0 after updating tail
` [PATCH v10 04/10] target/riscv/vector_helper.c: update tail with vext_set_tail_elems_1s()
` [PATCH v10 05/10] target/riscv: use vext_set_tail_elems_1s() in vcrypto insns
` [PATCH v10 06/10] trans_rvv.c.inc: set vstart = 0 in int scalar move insns
` [PATCH v10 07/10] target/riscv: remove 'over' brconds from vector trans
` [PATCH v10 08/10] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
` [PATCH v10 09/10] target/riscv: enable 'vstart_qe_zero' in the end of insns
` [PATCH v10 10/10] target/riscv/vector_helper.c: optimize loops in ldst helpers
[PATCH v8 00/10] riscv: set vstart_eq_zero on mark_vs_dirty
2024-03-09 20:24 UTC (15+ messages)
` [PATCH v8 01/10] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
` [PATCH v8 02/10] target/riscv: handle vstart >= vl in vext_set_tail_elems_1s()
` [PATCH v8 03/10] target/riscv/vector_helper.c: do vstart=0 after updating tail
` [PATCH v8 04/10] target/riscv/vector_helper.c: update tail with vext_set_tail_elems_1s()
` [PATCH v8 05/10] target/riscv: use vext_set_tail_elems_1s() in vcrypto insns
` [PATCH v8 06/10] trans_rvv.c.inc: set vstart = 0 in int scalar move insns
` [PATCH v8 07/10] target/riscv: remove 'over' brconds from vector trans
` [PATCH v8 08/10] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
` [PATCH v8 09/10] target/riscv: Clear vstart_qe_zero flag
` [PATCH v8 10/10] target/riscv/vector_helper.c: optimize loops in ldst helpers
[PATCH] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
2024-03-09 18:05 UTC (2+ messages)
[PATCH v2 00/20] Workaround Windows failing to find 64bit SMBIOS entry point with SeaBIOS
2024-03-09 5:42 UTC (8+ messages)
` [PATCH v2 07/20] smbios: avoid mangling user provided tables
` [PATCH v2 14/20] smbios: extend smbios-entry-point-type with 'auto' value
[PATCH 0/2] linux-user/riscv: Sync hwprobe keys with kernel
2024-03-08 13:15 UTC (4+ messages)
` [PATCH 2/2] linux-user/riscv: Sync hwprobe keys with Linux
[PATCH] target/riscv: Implement dynamic establishment of custom decoder
2024-03-08 11:56 UTC (7+ messages)
[PATCH v7 0/9] riscv: set vstart_eq_zero on mark_vs_dirty
2024-03-08 11:23 UTC (6+ messages)
` [PATCH v7 3/9] target/riscv: remove 'over' brconds from vector trans
[PATCH v2 00/15] riscv: QEMU RISC-V IOMMU Support
2024-03-07 16:03 UTC (16+ messages)
` [PATCH v2 01/15] exec/memtxattr: add process identifier to the transaction attributes
` [PATCH v2 02/15] hw/riscv: add riscv-iommu-bits.h
` [PATCH v2 03/15] hw/riscv: add RISC-V IOMMU base emulation
` [PATCH v2 04/15] hw/riscv: add riscv-iommu-pci device
` [PATCH v2 05/15] hw/riscv: add riscv-iommu-sys platform device
` [PATCH v2 06/15] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
` [PATCH v2 07/15] test/qtest: add riscv-iommu-pci tests
` [PATCH v2 08/15] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
` [PATCH v2 09/15] hw/riscv/riscv-iommu: add s-stage and g-stage support
` [PATCH v2 10/15] hw/riscv/riscv-iommu: add ATS support
` [PATCH v2 11/15] hw/riscv/riscv-iommu: add DBG support
` [PATCH v2 12/15] hw/riscv/riscv-iommu: Add another irq for mrif notifications
` [PATCH v2 13/15] qtest/riscv-iommu-test: add init queues test
` [PATCH v2 14/15] hw/misc: EDU: added PASID support
` [PATCH v2 15/15] hw/misc: EDU: add ATS/PRI capability
[PATCH] target/riscv/vector_helper.c: Avoid shifting negative in fractional LMUL checking
2024-03-07 14:54 UTC (3+ messages)
[PATCH v5 0/5] Add ISA extension smcntrpmf support
2024-03-07 9:27 UTC (7+ messages)
` [PATCH v5 2/5] target/riscv: Add cycle & instret privilege mode filtering properties
` [PATCH v5 5/5] target/riscv: Implement privilege mode filtering for cycle/instret
[PATCH v2 0/2] RISC-V: ACPI: Enable SPCR
2024-03-07 9:22 UTC (7+ messages)
` [PATCH v2 1/2] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location
[PATCH v4 0/4] RISC-V: Modularize common match conditions for trigger
2024-03-07 2:35 UTC (2+ messages)
[PATCH 0/2] RISC-V APLIC fixes
2024-03-07 2:28 UTC (2+ messages)
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