From: Alexandre Ghiti <alexghiti@rivosinc.com>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH RFC] target: riscv: Add Svvptc extension support
Date: Tue, 20 Feb 2024 23:05:05 +0100 [thread overview]
Message-ID: <CAHVXubjs87Tqqyx=BSBm3RqiwvsYGSG_Nn0F-XAH2coQJLtr1A@mail.gmail.com> (raw)
In-Reply-To: <20240213-87d669a3bd421a1b2bc30fc2@orel>
Hi Andrew,
Sorry for the very late reply, I was (and still am) off!
On Tue, Feb 13, 2024 at 4:33 PM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Tue, Feb 13, 2024 at 03:53:08PM +0100, Alexandre Ghiti wrote:
> > The Svvptc extension describes a uarch that does not cache invalid TLB
> > entries: that's the case for qemu so there is nothing particular to
> > implement other than the introduction of this extension, which is done
> > here.
> >
> > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> > ---
> >
> > That's an RFC since the extension has not been ratified yet.
>
> Hi Alex,
>
> No need for the RFC tag. You can add not-yet-ratified extension support
> to QEMU as long as the CPU property is off by default (as you've done)
> and you add it to the riscv_cpu_experimental_exts[] array with an "x-"
> prefix on its property name.
>
I'll do that next week then,
Thanks,
Alex
> Thanks,
> drew
>
> >
> > target/riscv/cpu.c | 2 ++
> > target/riscv/cpu_cfg.h | 1 +
> > 2 files changed, 3 insertions(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 1b8d001d23..4beb5d0350 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -178,6 +178,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
> > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
> > ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
> > + ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_12_0, ext_svvptc),
> > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
> > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
> > ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
> > @@ -1467,6 +1468,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> > MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
> > MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
> > MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
> > + MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, false),
> >
> > MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true),
> > MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true),
> > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> > index 833bf58217..c973693b6e 100644
> > --- a/target/riscv/cpu_cfg.h
> > +++ b/target/riscv/cpu_cfg.h
> > @@ -77,6 +77,7 @@ struct RISCVCPUConfig {
> > bool ext_svinval;
> > bool ext_svnapot;
> > bool ext_svpbmt;
> > + bool ext_svvptc;
> > bool ext_zdinx;
> > bool ext_zaamo;
> > bool ext_zacas;
> > --
> > 2.39.2
> >
> >
prev parent reply other threads:[~2024-02-20 22:05 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-13 14:53 [PATCH RFC] target: riscv: Add Svvptc extension support Alexandre Ghiti
2024-02-13 15:33 ` Andrew Jones
2024-02-20 22:05 ` Alexandre Ghiti [this message]
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