From: Alistair Francis <alistair23@gmail.com>
To: Vadim Shakirov <vadim.shakirov@syntacore.com>
Cc: qemu-devel@nongnu.org, Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
qemu-riscv@nongnu.org
Subject: Re: [PATCH v3] target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit
Date: Fri, 2 Feb 2024 13:30:31 +1000 [thread overview]
Message-ID: <CAKmqyKPc6K50usZFBgfPqCxTEUibzTmApWWuB=9t_7nN3_Wi2g@mail.gmail.com> (raw)
In-Reply-To: <20240131123624.230982-1-vadim.shakirov@syntacore.com>
On Wed, Jan 31, 2024 at 10:37 PM Vadim Shakirov
<vadim.shakirov@syntacore.com> wrote:
>
> mcountinhibit, mcounteren, scounteren and hcounteren must always be 32-bit
> by privileged spec
>
> Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com>
Do you mind rebasing this on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next ?
Alistair
> ---
> target/riscv/cpu.h | 8 ++++----
> target/riscv/machine.c | 16 ++++++++--------
> 2 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 5b0824ef8f..88efd8a6f9 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -254,7 +254,7 @@ struct CPUArchState {
> target_ulong hstatus;
> target_ulong hedeleg;
> uint64_t hideleg;
> - target_ulong hcounteren;
> + uint32_t hcounteren;
> target_ulong htval;
> target_ulong htinst;
> target_ulong hgatp;
> @@ -317,10 +317,10 @@ struct CPUArchState {
> */
> bool two_stage_indirect_lookup;
>
> - target_ulong scounteren;
> - target_ulong mcounteren;
> + uint32_t scounteren;
> + uint32_t mcounteren;
>
> - target_ulong mcountinhibit;
> + uint32_t mcountinhibit;
>
> /* PMU counter state */
> PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index fdde243e04..f129032b0d 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -79,14 +79,14 @@ static bool hyper_needed(void *opaque)
>
> static const VMStateDescription vmstate_hyper = {
> .name = "cpu/hyper",
> - .version_id = 3,
> - .minimum_version_id = 3,
> + .version_id = 4,
> + .minimum_version_id = 4,
> .needed = hyper_needed,
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL(env.hstatus, RISCVCPU),
> VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
> VMSTATE_UINT64(env.hideleg, RISCVCPU),
> - VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
> + VMSTATE_UINT32(env.hcounteren, RISCVCPU),
> VMSTATE_UINTTL(env.htval, RISCVCPU),
> VMSTATE_UINTTL(env.htinst, RISCVCPU),
> VMSTATE_UINTTL(env.hgatp, RISCVCPU),
> @@ -354,8 +354,8 @@ static const VMStateDescription vmstate_jvt = {
>
> const VMStateDescription vmstate_riscv_cpu = {
> .name = "cpu",
> - .version_id = 9,
> - .minimum_version_id = 9,
> + .version_id = 10,
> + .minimum_version_id = 10,
> .post_load = riscv_cpu_post_load,
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> @@ -398,9 +398,9 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.mtval, RISCVCPU),
> VMSTATE_UINTTL(env.miselect, RISCVCPU),
> VMSTATE_UINTTL(env.siselect, RISCVCPU),
> - VMSTATE_UINTTL(env.scounteren, RISCVCPU),
> - VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
> - VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
> + VMSTATE_UINT32(env.scounteren, RISCVCPU),
> + VMSTATE_UINT32(env.mcounteren, RISCVCPU),
> + VMSTATE_UINT32(env.mcountinhibit, RISCVCPU),
> VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
> vmstate_pmu_ctr_state, PMUCTRState),
> VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
> --
> 2.34.1
>
>
prev parent reply other threads:[~2024-02-02 3:31 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-31 12:36 [PATCH v3] target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit Vadim Shakirov
2024-01-31 13:37 ` Andrew Jones
2024-02-02 2:25 ` Alistair Francis
2024-02-02 3:30 ` Alistair Francis [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAKmqyKPc6K50usZFBgfPqCxTEUibzTmApWWuB=9t_7nN3_Wi2g@mail.gmail.com' \
--to=alistair23@gmail.com \
--cc=alistair.francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=dbarboza@ventanamicro.com \
--cc=liwei1518@gmail.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=vadim.shakirov@syntacore.com \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).