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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Irina Ryapolova <irina.ryapolova@syntacore.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
	alistair.francis@wdc.com, bin.meng@windriver.com,
	liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com
Subject: Re: [PATCH v2 1/2] target/riscv/csr.c: Add functional of hvictl CSR
Date: Wed, 20 Mar 2024 18:02:30 -0300	[thread overview]
Message-ID: <a116ce8f-1ee0-4bad-8d05-88cac66b8a7e@ventanamicro.com> (raw)
In-Reply-To: <20240320164259.19205-1-irina.ryapolova@syntacore.com>

Hi,

This patch doesn't apply in master or alistair/riscv-to-apply.next. Can you
please re-send?


Thanks,


Daniel


On 3/20/24 13:42, Irina Ryapolova wrote:
> CSR hvictl (Hypervisor Virtual Interrupt Control) provides further flexibility
> for injecting interrupts into VS level in situations not fully supported by the
> facilities described thus far, but only with more active involvement of the hypervisor.
> 
> A hypervisor must use hvictl for any of the following:
> • asserting for VS level a major interrupt not supported by hvien and hvip;
> • implementing configurability of priorities at VS level for major interrupts beyond those sup-
> ported by hviprio1 and hviprio2; or
> • emulating an external interrupt controller for a virtual hart without the use of an IMSIC’s
> guest interrupt file, while also supporting configurable priorities both for external interrupts
> and for major interrupts to the virtual hart.
> 
> All hvictl fields together can affect the value of CSR vstopi (Virtual Supervisor Top Interrupt)
> and therefore the interrupt identity reported in vscause when an interrupt traps to VS-mode.
> When hvictl.VTI = 1, the absence of an interrupt for VS level can be indicated only by setting
> hvictl.IID = 9. Software might want to use the pair IID = 9, IPRIO = 0 generally to represent
> no interrupt in hvictl.
> 
> (See riscv-interrupts-1.0: Interrupts at VS level)
> 
> Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
> ---
> Changes for v2:
>    -added more information in commit message
> ---
>   target/riscv/csr.c | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
> 
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 674ea075a4..0c21145eaf 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3585,6 +3585,21 @@ static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val)
>   static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val)
>   {
>       env->hvictl = val & HVICTL_VALID_MASK;
> +    if (env->hvictl & HVICTL_VTI)
> +    {
> +        uint32_t hviid = get_field(env->hvictl, HVICTL_IID);
> +        uint32_t hviprio = get_field(env->hvictl, HVICTL_IPRIO);
> +        /* the pair IID = 9, IPRIO = 0 generally to represent no interrupt in hvictl. */
> +        if (!(hviid == IRQ_S_EXT && hviprio == 0)) {
> +            uint64_t new_val = BIT(hviid) ;
> +             if (new_val & S_MODE_INTERRUPTS) {
> +                rmw_hvip64(env, csrno, NULL, new_val << 1, new_val << 1);
> +            } else if (new_val & LOCAL_INTERRUPTS) {
> +                rmw_hvip64(env, csrno, NULL, new_val, new_val);
> +            }
> +        }
> +    }
> +
>       return RISCV_EXCP_NONE;
>   }
>   

     prev parent reply	other threads:[~2024-03-20 21:03 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-20 16:42 [PATCH v2 1/2] target/riscv/csr.c: Add functional of hvictl CSR Irina Ryapolova
2024-03-20 16:42 ` [PATCH v2 2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS Irina Ryapolova
2024-03-20 21:02 ` Daniel Henrique Barboza [this message]

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