From: "Clément Léger" <cleger@rivosinc.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: qemu-riscv@nongnu.org, Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Ved Shanbhogue <ved@rivosinc.com>,
Atish Patra <atishp@rivosinc.com>,
qemu-devel@nongnu.org
Subject: Re: [RFC PATCH 1/3] target/riscv: change RISCV_EXCP_SEMIHOST exception number
Date: Mon, 22 Apr 2024 15:01:58 +0200 [thread overview]
Message-ID: <bdc875c7-4581-4608-a76d-3e3469a8bc9a@rivosinc.com> (raw)
In-Reply-To: <CAKmqyKOcYwAgEnV-gyUYu19dLCKx94-rMoaE5m-8FB0fq7AL+g@mail.gmail.com>
On 22/04/2024 05:25, Alistair Francis wrote:
> On Thu, Apr 18, 2024 at 11:40 PM Clément Léger <cleger@rivosinc.com> wrote:
>>
>> The double trap specification defines the double trap exception number
>> to be 16 which is actually used by the internal semihosting one. Change
>> it to some other value.
>>
>> Signed-off-by: Clément Léger <cleger@rivosinc.com>
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Hi Alistair,
Ved actually told me that even 17 is reserved so I'll move the semihost
one to 63, which is in a range designated for custom use.
Regards,
Clément
>
> Alistair
>
>> ---
>> target/riscv/cpu_bits.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
>> index fc2068ee4d..9ade72ff31 100644
>> --- a/target/riscv/cpu_bits.h
>> +++ b/target/riscv/cpu_bits.h
>> @@ -670,7 +670,7 @@ typedef enum RISCVException {
>> RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
>> RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
>> RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
>> - RISCV_EXCP_SEMIHOST = 0x10,
>> + RISCV_EXCP_SEMIHOST = 0x11,
>> RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
>> RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
>> RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
>> --
>> 2.43.0
>>
>>
next prev parent reply other threads:[~2024-04-22 13:02 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-18 13:39 [RFC PATCH 0/3] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions Clément Léger
2024-04-18 13:39 ` [RFC PATCH 1/3] target/riscv: change RISCV_EXCP_SEMIHOST exception number Clément Léger
2024-04-22 3:25 ` Alistair Francis
2024-04-22 13:01 ` Clément Léger [this message]
2024-04-18 13:39 ` [RFC PATCH 2/3] target/riscv: add Ssdbltrp extension support Clément Léger
2024-04-18 13:39 ` [RFC PATCH 3/3] target/riscv: add Smdbltrp " Clément Léger
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