From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Jason Chien <jason.chien@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Frank Chang <frank.chang@sifive.com>,
Max Chou <max.chou@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liwei1518@gmail.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH 4/5] target/riscv: Expose Zve64x extension to users
Date: Thu, 21 Mar 2024 09:20:54 -0300 [thread overview]
Message-ID: <f9aed9be-75bb-40e7-83af-0fd4161fce9e@ventanamicro.com> (raw)
In-Reply-To: <20240306170855.24341-5-jason.chien@sifive.com>
On 3/6/24 14:08, Jason Chien wrote:
> Signed-off-by: Jason Chien <jason.chien@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Max Chou <max.chou@sifive.com>
> ---
Please add the following tag in this commit msg:
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
The link is a feature request named "target/riscv: zve32x/zve64x are not supported"
that was opened a couple of months ago. Adding this tag will close the bug (since by
this time we'll have both zve32x and zve64x) as soon as the series is merged to
master.
Thanks,
Daniel
> target/riscv/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8b5d1eb6a8..58b2a94694 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1473,6 +1473,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
> MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
> MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
> + MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
> MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
>
> MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
next prev parent reply other threads:[~2024-03-21 12:21 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-06 17:08 [PATCH 0/5] target/riscv: Support Zve32x and Zve64x extensions Jason Chien
2024-03-06 17:08 ` [PATCH 1/5] target/riscv: Add support for Zve32x extension Jason Chien
2024-03-19 16:23 ` Jason Chien
2024-03-19 21:19 ` Daniel Henrique Barboza
2024-03-21 7:06 ` Jason Chien
2024-03-06 17:08 ` [PATCH 2/5] target/riscv: Expose Zve32x extension to users Jason Chien
2024-03-06 17:08 ` [PATCH 3/5] target/riscv: Add support for Zve64x extension Jason Chien
2024-03-06 17:08 ` [PATCH 4/5] target/riscv: Expose Zve64x extension to users Jason Chien
2024-03-21 12:20 ` Daniel Henrique Barboza [this message]
2024-03-06 17:08 ` [PATCH 5/5] target/riscv: Relax vector register check in RISCV gdbstub Jason Chien
2024-03-19 16:23 ` [PATCH 0/5] target/riscv: Support Zve32x and Zve64x extensions Jason Chien
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=f9aed9be-75bb-40e7-83af-0fd4161fce9e@ventanamicro.com \
--to=dbarboza@ventanamicro.com \
--cc=alistair.francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=frank.chang@sifive.com \
--cc=jason.chien@sifive.com \
--cc=liwei1518@gmail.com \
--cc=max.chou@sifive.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).