From: Hal Feng <hal.feng@starfivetech.com>
To: Bo Gan <ganboing@gmail.com>,
"rick@andestech.com" <rick@andestech.com>,
"ycliang@andestech.com" <ycliang@andestech.com>,
"trini@konsulko.com" <trini@konsulko.com>,
"yanhong.wang@starfivetech.com" <yanhong.wang@starfivetech.com>,
Minda Chen <minda.chen@starfivetech.com>,
"duwe@suse.de" <duwe@suse.de>,
"namcao@linutronix.de" <namcao@linutronix.de>,
Xingyu Wu <xingyu.wu@starfivetech.com>,
Mason Huo <mason.huo@starfivetech.com>,
"chanho61.park@samsung.com" <chanho61.park@samsung.com>,
"u-boot@lists.denx.de" <u-boot@lists.denx.de>
Subject: RE: [PATCH] riscv: dts: jh7110: Enable PLL node in SPL
Date: Tue, 12 Mar 2024 06:09:27 +0000 [thread overview]
Message-ID: <ZQ2PR01MB13079F11D2A7B2A20968F4FDE62BA@ZQ2PR01MB1307.CHNPR01.prod.partner.outlook.cn> (raw)
In-Reply-To: <1709694011-683-1-git-send-email-ganboing@gmail.com>
> On 06.03.24 11:00, Bo Gan wrote:
>
> Previously PLL node was missing from SPL dts. This caused BUS_ROOT to stay on
> OSC clock (24Mhz). As a result, all peripherals have to run at a much lower
> frequency, and loading from sdcard/emmc is slow.
> Thus, enabling PLL node in dts to fix this.
>
> Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
next prev parent reply other threads:[~2024-03-12 11:12 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-06 3:00 [PATCH] riscv: dts: jh7110: Enable PLL node in SPL Bo Gan
2024-03-12 5:12 ` Leo Liang
2024-03-12 6:09 ` Hal Feng [this message]
2024-04-10 1:55 ` E Shattow
2024-04-10 6:44 ` Bo Gan
2024-04-17 4:59 ` E Shattow
2024-04-20 0:51 ` Bo Gan
2024-04-20 10:56 ` E Shattow
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