From: Bo Gan <ganboing@gmail.com>
To: E Shattow <lucent@gmail.com>, Bo Gan <ganboing@gmail.com>
Cc: Hal Feng <hal.feng@starfivetech.com>,
"rick@andestech.com" <rick@andestech.com>,
"ycliang@andestech.com" <ycliang@andestech.com>,
"trini@konsulko.com" <trini@konsulko.com>,
"yanhong.wang@starfivetech.com" <yanhong.wang@starfivetech.com>,
Minda Chen <minda.chen@starfivetech.com>,
"duwe@suse.de" <duwe@suse.de>,
"namcao@linutronix.de" <namcao@linutronix.de>,
Xingyu Wu <xingyu.wu@starfivetech.com>,
Mason Huo <mason.huo@starfivetech.com>,
"chanho61.park@samsung.com" <chanho61.park@samsung.com>,
"u-boot@lists.denx.de" <u-boot@lists.denx.de>
Subject: Re: [PATCH] riscv: dts: jh7110: Enable PLL node in SPL
Date: Fri, 19 Apr 2024 17:51:05 -0700 [thread overview]
Message-ID: <f355e582-cb52-e4c5-538b-26bcf69f0a2c@gmail.com> (raw)
In-Reply-To: <CANV2PTP3o1Q2JPCZO8Ewfye+oz9f3TVNTYhYZ3EAKtdYAhvkHg@mail.gmail.com>
On 4/16/24 9:59 PM, E Shattow wrote:
> On Tue, Apr 9, 2024 at 11:44 PM Bo Gan <ganboing@gmail.com> wrote:
>>
>> On 4/9/24 6:55 PM, E Shattow wrote:
>>> Original speed class SD cards fail with this change "unable to change mode".
>>>
>>
>> The BUS_ROOT clock will have to be switched to PLL2 anyway in U-Boot proper or
>> in Linux, because it's the parent or grandparent clock for *lots* of devices,
>> including PCIe, i2c, spi, qspi... If there's an issue with this change, then
>> I suspect there's something wrong with the dw_mmc driver.
>>
>> Bo
>
> I've bisected and can confirm this change is what breaks original
> speed SD function on Milk-V Mars CM Lite (DFRobot mini router
> carrier). Class 10 speed SD media does not seem to be affected.
> Reverting the change allows the original speed SD media access to
> function again. SD access is functional in Linux with and without the
> change.
>
> How to troubleshoot this?
>
> Thanks,
>
> E
>
If without the change (reverted), can you read/write the same SD media in U-boot
proper? (U-boot proper will switch BUS_ROOT to PLL2). One potential problem I
could think of is perhaps the SPL built is without SPL_PINCTRL_STARFIVE/JH7110
or the u-boot dts is missing the pinctrl that properly sets drive-strength and
other properties of the mmc0/1 pins. What dtb are you using? I tested this with
visionfive2 and it's working fine. Can you share the tree/config you used to
built for Milk-V Mars CM Lite? I don't see the corresponding dts being checked-
in to u-boot tree, so it helps if you can share the code. Thanks!
Bo
next prev parent reply other threads:[~2024-04-20 0:51 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-06 3:00 [PATCH] riscv: dts: jh7110: Enable PLL node in SPL Bo Gan
2024-03-12 5:12 ` Leo Liang
2024-03-12 6:09 ` Hal Feng
2024-04-10 1:55 ` E Shattow
2024-04-10 6:44 ` Bo Gan
2024-04-17 4:59 ` E Shattow
2024-04-20 0:51 ` Bo Gan [this message]
2024-04-20 10:56 ` E Shattow
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