From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 13/24] target-arm: Use tcg_gen_extrh_i64_i32
Date: Mon, 14 Sep 2015 14:53:00 +0100 [thread overview]
Message-ID: <1442238791-30255-14-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1442238791-30255-1-git-send-email-peter.maydell@linaro.org>
From: Richard Henderson <rth@twiddle.net>
Usually, eliminate an operation from the translator by combining
a shift with an extract.
In the case of gen_set_NZ64, we don't need a boolean value for cpu_ZF,
merely a non-zero value. Given that we can extract both halves of a
64-bit input in one call, this simplifies the code.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-id: 1441909103-24666-12-git-send-email-rth@twiddle.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/translate-a64.c | 34 +++++++++-------------------------
1 file changed, 9 insertions(+), 25 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 04e7479..ec0936c 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -529,13 +529,8 @@ static TCGv_ptr get_fpstatus_ptr(void)
*/
static inline void gen_set_NZ64(TCGv_i64 result)
{
- TCGv_i64 flag = tcg_temp_new_i64();
-
- tcg_gen_setcondi_i64(TCG_COND_NE, flag, result, 0);
- tcg_gen_extrl_i64_i32(cpu_ZF, flag);
- tcg_gen_shri_i64(flag, result, 32);
- tcg_gen_extrl_i64_i32(cpu_NF, flag);
- tcg_temp_free_i64(flag);
+ tcg_gen_extr_i64_i32(cpu_ZF, cpu_NF, result);
+ tcg_gen_or_i32(cpu_ZF, cpu_ZF, cpu_NF);
}
/* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
@@ -545,7 +540,7 @@ static inline void gen_logic_CC(int sf, TCGv_i64 result)
gen_set_NZ64(result);
} else {
tcg_gen_extrl_i64_i32(cpu_ZF, result);
- tcg_gen_extrl_i64_i32(cpu_NF, result);
+ tcg_gen_mov_i32(cpu_NF, cpu_ZF);
}
tcg_gen_movi_i32(cpu_CF, 0);
tcg_gen_movi_i32(cpu_VF, 0);
@@ -571,8 +566,7 @@ static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
tcg_gen_xor_i64(tmp, t0, t1);
tcg_gen_andc_i64(flag, flag, tmp);
tcg_temp_free_i64(tmp);
- tcg_gen_shri_i64(flag, flag, 32);
- tcg_gen_extrl_i64_i32(cpu_VF, flag);
+ tcg_gen_extrh_i64_i32(cpu_VF, flag);
tcg_gen_mov_i64(dest, result);
tcg_temp_free_i64(result);
@@ -620,8 +614,7 @@ static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
tcg_gen_xor_i64(tmp, t0, t1);
tcg_gen_and_i64(flag, flag, tmp);
tcg_temp_free_i64(tmp);
- tcg_gen_shri_i64(flag, flag, 32);
- tcg_gen_extrl_i64_i32(cpu_VF, flag);
+ tcg_gen_extrh_i64_i32(cpu_VF, flag);
tcg_gen_mov_i64(dest, result);
tcg_temp_free_i64(flag);
tcg_temp_free_i64(result);
@@ -680,8 +673,7 @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
tcg_gen_xor_i64(vf_64, result, t0);
tcg_gen_xor_i64(tmp, t0, t1);
tcg_gen_andc_i64(vf_64, vf_64, tmp);
- tcg_gen_shri_i64(vf_64, vf_64, 32);
- tcg_gen_extrl_i64_i32(cpu_VF, vf_64);
+ tcg_gen_extrh_i64_i32(cpu_VF, vf_64);
tcg_gen_mov_i64(dest, result);
@@ -7775,10 +7767,8 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
} else {
TCGv_i32 tcg_lo = tcg_temp_new_i32();
TCGv_i32 tcg_hi = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(tcg_lo, tcg_op);
+ tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op);
gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, cpu_env);
- tcg_gen_shri_i64(tcg_op, tcg_op, 32);
- tcg_gen_extrl_i64_i32(tcg_hi, tcg_op);
gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, cpu_env);
tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16);
tcg_temp_free_i32(tcg_lo);
@@ -8684,16 +8674,10 @@ static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size,
}
}
-static void do_narrow_high_u32(TCGv_i32 res, TCGv_i64 in)
-{
- tcg_gen_shri_i64(in, in, 32);
- tcg_gen_extrl_i64_i32(res, in);
-}
-
static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in)
{
tcg_gen_addi_i64(in, in, 1U << 31);
- do_narrow_high_u32(res, in);
+ tcg_gen_extrh_i64_i32(res, in);
}
static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,
@@ -8712,7 +8696,7 @@ static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,
gen_helper_neon_narrow_round_high_u8 },
{ gen_helper_neon_narrow_high_u16,
gen_helper_neon_narrow_round_high_u16 },
- { do_narrow_high_u32, do_narrow_round_high_u32 },
+ { tcg_gen_extrh_i64_i32, do_narrow_round_high_u32 },
};
NeonGenNarrowFn *gennarrow = narrowfns[size][is_u];
--
1.9.1
next prev parent reply other threads:[~2015-09-14 13:53 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-14 13:52 [Qemu-devel] [PULL 00/24] target-arm queue Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 01/24] arm: xlnx-zynqmp: Fix up GIC region size Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 02/24] xlnx-zynqmp: Remove unnecessary brackets around error messages Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 03/24] target-arm: Share all common TCG temporaries Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 04/24] target-arm: Introduce DisasCompare Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 05/24] target-arm: Handle always condition codes within arm_test_cc Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 06/24] target-arm: Use setcond and movcond for csel Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 07/24] target-arm: Implement ccmp branchless Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 08/24] target-arm: Implement fcsel with movcond Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 09/24] target-arm: Recognize SXTB, SXTH, SXTW, ASR Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 10/24] target-arm: Recognize UXTB, UXTH, LSR, LSL Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 11/24] target-arm: Eliminate unnecessary zero-extend in disas_bitfield Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 12/24] target-arm: Recognize ROR Peter Maydell
2015-09-14 13:53 ` Peter Maydell [this message]
2015-09-14 13:53 ` [Qemu-devel] [PULL 14/24] i.MX: Add GPIO device Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 15/24] i.MX: Add GPIO devices to i.MX31 SOC Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 16/24] i.MX: Add GPIO devices to i.MX25 SOC Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 17/24] hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 18/24] target-arm: Add VTCR_EL2 Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 19/24] target-arm: Add VTTBR_EL2 Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 20/24] target-arm: Suppress TBI for S2 translations Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 21/24] target-arm: Suppress EPD for S2, EL2 and EL3 translations Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 22/24] target-arm: Add VPIDR_EL2 Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 23/24] target-arm: Break out mpidr_read_val() Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 24/24] target-arm: Add VMPIDR_EL2 Peter Maydell
2015-09-14 15:12 ` [Qemu-devel] [PULL 00/24] target-arm queue Peter Maydell
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