From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 03/24] target-arm: Share all common TCG temporaries
Date: Mon, 14 Sep 2015 14:52:50 +0100 [thread overview]
Message-ID: <1442238791-30255-4-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1442238791-30255-1-git-send-email-peter.maydell@linaro.org>
From: Richard Henderson <rth@twiddle.net>
This is a bug fix for aarch64. At present, we have branches using
the 32-bit (translate.c) versions of cpu_[NZCV]F, but we set the flags
using the 64-bit (translate-a64.c) versions of cpu_[NZCV]F. From
the view of the TCG code generator, these are unrelated variables.
The bug is hard to see because we currently only read these variables
from branches, and upon reaching a branch TCG will first spill live
variables and then reload the arguments of the branch. Since the
32-bit versions were never live until reaching the branch, we'd re-read
the data that had just been spilled from the 64-bit versions.
There is currently no such problem with the cpu_exclusive_* variables,
but there's no point in tempting fate.
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-id: 1441909103-24666-2-git-send-email-rth@twiddle.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/translate-a64.c | 22 ----------------------
target-arm/translate.c | 10 +++++-----
target-arm/translate.h | 8 ++++++++
3 files changed, 13 insertions(+), 27 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index faece2c..bb70185 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -40,16 +40,9 @@
static TCGv_i64 cpu_X[32];
static TCGv_i64 cpu_pc;
-static TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
/* Load/store exclusive handling */
-static TCGv_i64 cpu_exclusive_addr;
-static TCGv_i64 cpu_exclusive_val;
static TCGv_i64 cpu_exclusive_high;
-#ifdef CONFIG_USER_ONLY
-static TCGv_i64 cpu_exclusive_test;
-static TCGv_i32 cpu_exclusive_info;
-#endif
static const char *regnames[] = {
"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
@@ -105,23 +98,8 @@ void a64_translate_init(void)
regnames[i]);
}
- cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF), "NF");
- cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF), "ZF");
- cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF), "CF");
- cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF), "VF");
-
- cpu_exclusive_addr = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
- cpu_exclusive_val = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUARMState, exclusive_val), "exclusive_val");
cpu_exclusive_high = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUARMState, exclusive_high), "exclusive_high");
-#ifdef CONFIG_USER_ONLY
- cpu_exclusive_test = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUARMState, exclusive_test), "exclusive_test");
- cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUARMState, exclusive_info), "exclusive_info");
-#endif
}
static inline ARMMMUIdx get_a64_user_mem_index(DisasContext *s)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index ae70577..f1b7c16 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -64,12 +64,12 @@ TCGv_ptr cpu_env;
/* We reuse the same 64-bit temporaries for efficiency. */
static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
static TCGv_i32 cpu_R[16];
-static TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
-static TCGv_i64 cpu_exclusive_addr;
-static TCGv_i64 cpu_exclusive_val;
+TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
+TCGv_i64 cpu_exclusive_addr;
+TCGv_i64 cpu_exclusive_val;
#ifdef CONFIG_USER_ONLY
-static TCGv_i64 cpu_exclusive_test;
-static TCGv_i32 cpu_exclusive_info;
+TCGv_i64 cpu_exclusive_test;
+TCGv_i32 cpu_exclusive_info;
#endif
/* FIXME: These should be removed. */
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 4b618a4..a30a1db3 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -63,7 +63,15 @@ typedef struct DisasContext {
TCGv_i64 tmp_a64[TMP_A64_MAX];
} DisasContext;
+/* Share the TCG temporaries common between 32 and 64 bit modes. */
extern TCGv_ptr cpu_env;
+extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
+extern TCGv_i64 cpu_exclusive_addr;
+extern TCGv_i64 cpu_exclusive_val;
+#ifdef CONFIG_USER_ONLY
+extern TCGv_i64 cpu_exclusive_test;
+extern TCGv_i32 cpu_exclusive_info;
+#endif
static inline int arm_dc_feature(DisasContext *dc, int feature)
{
--
1.9.1
next prev parent reply other threads:[~2015-09-14 13:53 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-14 13:52 [Qemu-devel] [PULL 00/24] target-arm queue Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 01/24] arm: xlnx-zynqmp: Fix up GIC region size Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 02/24] xlnx-zynqmp: Remove unnecessary brackets around error messages Peter Maydell
2015-09-14 13:52 ` Peter Maydell [this message]
2015-09-14 13:52 ` [Qemu-devel] [PULL 04/24] target-arm: Introduce DisasCompare Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 05/24] target-arm: Handle always condition codes within arm_test_cc Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 06/24] target-arm: Use setcond and movcond for csel Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 07/24] target-arm: Implement ccmp branchless Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 08/24] target-arm: Implement fcsel with movcond Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 09/24] target-arm: Recognize SXTB, SXTH, SXTW, ASR Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 10/24] target-arm: Recognize UXTB, UXTH, LSR, LSL Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 11/24] target-arm: Eliminate unnecessary zero-extend in disas_bitfield Peter Maydell
2015-09-14 13:52 ` [Qemu-devel] [PULL 12/24] target-arm: Recognize ROR Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 13/24] target-arm: Use tcg_gen_extrh_i64_i32 Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 14/24] i.MX: Add GPIO device Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 15/24] i.MX: Add GPIO devices to i.MX31 SOC Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 16/24] i.MX: Add GPIO devices to i.MX25 SOC Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 17/24] hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 18/24] target-arm: Add VTCR_EL2 Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 19/24] target-arm: Add VTTBR_EL2 Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 20/24] target-arm: Suppress TBI for S2 translations Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 21/24] target-arm: Suppress EPD for S2, EL2 and EL3 translations Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 22/24] target-arm: Add VPIDR_EL2 Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 23/24] target-arm: Break out mpidr_read_val() Peter Maydell
2015-09-14 13:53 ` [Qemu-devel] [PULL 24/24] target-arm: Add VMPIDR_EL2 Peter Maydell
2015-09-14 15:12 ` [Qemu-devel] [PULL 00/24] target-arm queue Peter Maydell
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