From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 24/24] arm: Remove workarounds for old M-profile exception return implementation
Date: Thu, 20 Apr 2017 17:41:10 +0100 [thread overview]
Message-ID: <1492706470-10921-25-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1492706470-10921-1-git-send-email-peter.maydell@linaro.org>
Now that we've rewritten M-profile exception return so that the magic
PC values are not visible to other parts of QEMU, we can delete the
special casing of them elsewhere.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1491844419-12485-10-git-send-email-peter.maydell@linaro.org
---
target/arm/cpu.c | 43 ++-----------------------------------------
target/arm/translate.c | 8 --------
2 files changed, 2 insertions(+), 49 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 04b062c..b357aee 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -304,33 +304,6 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-static void arm_v7m_unassigned_access(CPUState *cpu, hwaddr addr,
- bool is_write, bool is_exec, int opaque,
- unsigned size)
-{
- ARMCPU *arm = ARM_CPU(cpu);
- CPUARMState *env = &arm->env;
-
- /* ARMv7-M interrupt return works by loading a magic value into the PC.
- * On real hardware the load causes the return to occur. The qemu
- * implementation performs the jump normally, then does the exception
- * return by throwing a special exception when when the CPU tries to
- * execute code at the magic address.
- */
- if (env->v7m.exception != 0 && addr >= 0xfffffff0 && is_exec) {
- cpu->exception_index = EXCP_EXCEPTION_EXIT;
- cpu_loop_exit(cpu);
- }
-
- /* In real hardware an attempt to access parts of the address space
- * with nothing there will usually cause an external abort.
- * However our QEMU board models are often missing device models where
- * the guest can boot anyway with the default read-as-zero/writes-ignored
- * behaviour that you get without a QEMU unassigned_access hook.
- * So just return here to retain that default behaviour.
- */
-}
-
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -338,17 +311,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
CPUARMState *env = &cpu->env;
bool ret = false;
- /* ARMv7-M interrupt return works by loading a magic value
- * into the PC. On real hardware the load causes the
- * return to occur. The qemu implementation performs the
- * jump normally, then does the exception return when the
- * CPU tries to execute code at the magic address.
- * This will cause the magic PC value to be pushed to
- * the stack if an interrupt occurred at the wrong time.
- * We avoid this by disabling interrupts when
- * pc contains a magic address.
- *
- * ARMv7-M interrupt masking works differently than -A or -R.
+ /* ARMv7-M interrupt masking works differently than -A or -R.
* There is no FIQ/IRQ distinction. Instead of I and F bits
* masking FIQ and IRQ interrupts, an exception is taken only
* if it is higher priority than the current execution priority
@@ -356,8 +319,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
* currently active exception).
*/
if (interrupt_request & CPU_INTERRUPT_HARD
- && (armv7m_nvic_can_take_pending_exception(env->nvic))
- && (env->regs[15] < 0xfffffff0)) {
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
cs->exception_index = EXCP_IRQ;
cc->do_interrupt(cs);
ret = true;
@@ -1091,7 +1053,6 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = arm_v7m_cpu_do_interrupt;
#endif
- cc->do_unassigned_access = arm_v7m_unassigned_access;
cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index da03e153..0b5a0bc 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -11927,14 +11927,6 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
dc->is_jmp = DISAS_EXC;
break;
}
-#else
- if (arm_dc_feature(dc, ARM_FEATURE_M)) {
- /* Branches to the magic exception-return addresses should
- * already have been caught via the arm_v7m_unassigned_access hook,
- * and never get here.
- */
- assert(dc->pc < 0xfffffff0);
- }
#endif
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
--
2.7.4
next prev parent reply other threads:[~2017-04-20 16:41 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-20 16:40 [Qemu-devel] [PULL 00/24] target-arm queue Peter Maydell
2017-04-20 16:40 ` [Qemu-devel] [PULL 01/24] hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account Peter Maydell
2017-04-20 16:40 ` [Qemu-devel] [PULL 02/24] hw/arm/exynos: Convert fprintf to qemu_log_mask/error_report Peter Maydell
2017-04-20 16:40 ` [Qemu-devel] [PULL 03/24] hw/char/exynos4210_uart: Constify static array and few arguments Peter Maydell
2017-04-20 16:40 ` [Qemu-devel] [PULL 04/24] hw/misc/exynos4210_pmu: Reorder local variables for readability Peter Maydell
2017-04-20 16:40 ` [Qemu-devel] [PULL 05/24] target/arm: Add missing entries to excnames[] for log strings Peter Maydell
2017-04-20 16:40 ` [Qemu-devel] [PULL 06/24] arm: Move excnames[] array into arm_log_exceptions() Peter Maydell
2017-04-20 16:40 ` [Qemu-devel] [PULL 07/24] target/arm: Add assertion about FSC format for syndrome registers Peter Maydell
2017-04-20 16:40 ` [Qemu-devel] [PULL 08/24] stellaris: Don't hw_error() on bad register accesses Peter Maydell
2017-04-20 16:40 ` [Qemu-devel] [PULL 09/24] arm/kvm: Remove trailing newlines from error_report() Peter Maydell
2017-04-20 16:40 ` [Qemu-devel] [PULL 10/24] hw/arm: Qomify pxa2xx.c Peter Maydell
2017-04-20 16:40 ` [Qemu-devel] [PULL 11/24] cadence_gem: Read the correct queue descriptor Peter Maydell
2017-04-20 16:40 ` [Qemu-devel] [PULL 12/24] cadence_gem: Correct the multi-queue can rx logic Peter Maydell
2017-04-20 16:40 ` [Qemu-devel] [PULL 13/24] cadence_gem: Correct the interupt logic Peter Maydell
2017-04-20 16:41 ` [Qemu-devel] [PULL 14/24] cadence_gem: Make the revision a property Peter Maydell
2017-04-20 16:41 ` [Qemu-devel] [PULL 15/24] xlnx-zynqmp: Set the Cadence GEM revision Peter Maydell
2017-04-20 16:41 ` [Qemu-devel] [PULL 16/24] arm: Don't implement BXJ on M-profile CPUs Peter Maydell
2017-04-20 16:41 ` [Qemu-devel] [PULL 17/24] arm: Thumb shift operations should not permit interworking branches Peter Maydell
2017-04-20 16:41 ` [Qemu-devel] [PULL 18/24] arm: Factor out "generate right kind of step exception" Peter Maydell
2017-04-20 16:41 ` [Qemu-devel] [PULL 19/24] arm: Move gen_set_condexec() and gen_set_pc_im() up in the file Peter Maydell
2017-04-20 16:41 ` [Qemu-devel] [PULL 20/24] arm: Move condition-failed codepath generation out of if() Peter Maydell
2017-04-20 16:41 ` [Qemu-devel] [PULL 21/24] arm: Abstract out "are we singlestepping" test to utility function Peter Maydell
2017-04-20 16:41 ` [Qemu-devel] [PULL 22/24] arm: Track M profile handler mode state in TB flags Peter Maydell
2017-04-20 16:41 ` [Qemu-devel] [PULL 23/24] arm: Implement M profile exception return properly Peter Maydell
2017-04-20 16:41 ` Peter Maydell [this message]
2017-04-20 17:30 ` [Qemu-devel] [PULL 00/24] target-arm queue Peter Maydell
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