From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com,
LIU Zhiwei <zhiwei_liu@c-sky.com>,
wxy194768@alibaba-inc.com
Subject: [RFC PATCH 10/11] target/riscv: Update interrupt handling in CLIC mode
Date: Fri, 9 Apr 2021 15:48:56 +0800 [thread overview]
Message-ID: <20210409074857.166082-11-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com>
Decode CLIC interrupt information from exccode, includes interrupt
priviledge mode, interrupt level, and irq number.
Then update CSRs xcause, xstatus, xepc, xintstatus and jump to
correct PC according to the CLIC specification.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 117 +++++++++++++++++++++++++++++++++++---
2 files changed, 111 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 494e41edc9..d8378d2384 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -557,6 +557,7 @@
#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16
#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17
+#define RISCV_EXCP_INT_CLIC 0x40000000
#define RISCV_EXCP_INT_FLAG 0x80000000
#define RISCV_EXCP_INT_MASK 0x7fffffff
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 21c54ef561..998d1a2742 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -26,6 +26,10 @@
#include "trace.h"
#include "semihosting/common-semi.h"
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/intc/riscv_clic.h"
+#endif
+
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
@@ -36,6 +40,20 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
}
#ifndef CONFIG_USER_ONLY
+static int riscv_cpu_local_irq_mode_enabled(CPURISCVState *env, int mode)
+{
+ switch (mode) {
+ case PRV_M:
+ return env->priv < PRV_M ||
+ (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE));
+ case PRV_S:
+ return env->priv < PRV_S ||
+ (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
+ default:
+ return false;
+ }
+}
+
static int riscv_cpu_local_irq_pending(CPURISCVState *env)
{
target_ulong irqs;
@@ -90,6 +108,18 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return true;
}
}
+ if (interrupt_request & CPU_INTERRUPT_CLIC) {
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ int mode = (env->exccode >> 12) & 0b11;
+ int enabled = riscv_cpu_local_irq_mode_enabled(env, mode);
+ if (enabled) {
+ cs->exception_index = RISCV_EXCP_INT_CLIC | env->exccode;
+ cs->interrupt_request = cs->interrupt_request & ~CPU_INTERRUPT_CLIC;
+ riscv_cpu_do_interrupt(cs);
+ return true;
+ }
+ }
#endif
return false;
}
@@ -884,6 +914,55 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
#endif
}
+
+#if !defined(CONFIG_USER_ONLY)
+static target_ulong riscv_intr_pc(CPURISCVState *env, target_ulong tvec,
+ target_ulong tvt, bool async, bool clic,
+ int cause, int mode)
+{
+ int mode1 = tvec & 0b11, mode2 = tvec & 0b111111;
+ CPUState *cs = env_cpu(env);
+
+ if (!(async || clic)) {
+ return tvec & ~0b11;
+ }
+ /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
+ switch (mode1) {
+ case 0b00:
+ return tvec & ~0b11;
+ case 0b01:
+ return (tvec & ~0b11) + cause * 4;
+ default:
+ if (env->clic && (mode2 == 0b000011)) {
+ /* Non-vectored, clicintattr[i].shv = 0 || cliccfg.nvbits = 0 */
+ if (!riscv_clic_shv_interrupt(env->clic, mode, cs->cpu_index,
+ cause)) {
+ /* NBASE = mtvec[XLEN-1:6]<<6 */
+ return tvec & ~0b111111;
+ } else {
+ /*
+ * pc := M[TBASE + XLEN/8 * exccode)] & ~1,
+ * TBASE = mtvt[XLEN-1:6]<<6
+ */
+ int size = TARGET_LONG_BITS / 8;
+ target_ulong tbase = (tvt & ~0b111111) + size * cause;
+ void *host = tlb_vaddr_to_host(env, tbase, MMU_DATA_LOAD, mode);
+ if (host != NULL) {
+ target_ulong new_pc = ldn_p(host, size);
+ if (tlb_vaddr_to_host(env, new_pc, MMU_INST_FETCH, mode)) {
+ return new_pc;
+ }
+ }
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "CLIC: load trap handler error!\n");
+ exit(1);
+ }
+ }
+ g_assert_not_reached();
+ }
+}
+#endif
+
/*
* Handle Traps
*
@@ -898,11 +977,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
CPURISCVState *env = &cpu->env;
bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env);
uint64_t s;
+ int mode, level;
/* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
* so we mask off the MSB and separate into trap type and cause.
*/
bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
+ bool clic = !!(cs->exception_index & RISCV_EXCP_INT_CLIC);
target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
target_ulong deleg = async ? env->mideleg : env->medeleg;
bool write_tval = false;
@@ -958,6 +1039,28 @@ void riscv_cpu_do_interrupt(CPUState *cs)
}
}
+ if (clic) {
+ mode = (cause >> 12) & 3;
+ level = (cause >> 14) & 0xff;
+ cause &= 0xfff;
+ cause |= get_field(env->mstatus, MSTATUS_MPP) << 28;
+ switch (mode) {
+ case PRV_M:
+ cause |= get_field(env->mintstatus, MINTSTATUS_MIL) << 16;
+ cause |= get_field(env->mstatus, MSTATUS_MIE) << 27;
+ env->mintstatus = set_field(env->mintstatus, MINTSTATUS_MIL, level);
+ break;
+ case PRV_S:
+ cause |= get_field(env->mintstatus, MINTSTATUS_SIL) << 16;
+ cause |= get_field(env->mstatus, MSTATUS_SPIE) << 27;
+ env->mintstatus = set_field(env->mintstatus, MINTSTATUS_SIL, level);
+ break;
+ }
+ } else {
+ mode = env->priv <= PRV_S &&
+ cause < TARGET_LONG_BITS && ((deleg >> cause) & 1) ? PRV_S : PRV_M;
+ }
+
trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
riscv_cpu_get_trap_name(cause, async));
@@ -967,8 +1070,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
__func__, env->mhartid, async, cause, env->pc, tval,
riscv_cpu_get_trap_name(cause, async));
- if (env->priv <= PRV_S &&
- cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
+ if (mode == PRV_S) {
/* handle the trap in S-mode */
if (riscv_has_ext(env, RVH)) {
target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
@@ -1021,12 +1123,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
- env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
+ env->scause = cause | ((target_ulong)(async | clic) <<
+ (TARGET_LONG_BITS - 1));
env->sepc = env->pc;
env->sbadaddr = tval;
env->htval = htval;
- env->pc = (env->stvec >> 2 << 2) +
- ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
+ env->pc = riscv_intr_pc(env, env->stvec, env->stvt, async,
+ clic & 0xfff, cause, PRV_S);
riscv_cpu_set_mode(env, PRV_S);
} else {
/* handle the trap in M-mode */
@@ -1056,8 +1159,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->mepc = env->pc;
env->mbadaddr = tval;
env->mtval2 = mtval2;
- env->pc = (env->mtvec >> 2 << 2) +
- ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
+ env->pc = riscv_intr_pc(env, env->mtvec, env->mtvt, async,
+ clic, cause & 0xfff, PRV_M);
riscv_cpu_set_mode(env, PRV_M);
}
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com,
wxy194768@alibaba-inc.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [RFC PATCH 10/11] target/riscv: Update interrupt handling in CLIC mode
Date: Fri, 9 Apr 2021 15:48:56 +0800 [thread overview]
Message-ID: <20210409074857.166082-11-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com>
Decode CLIC interrupt information from exccode, includes interrupt
priviledge mode, interrupt level, and irq number.
Then update CSRs xcause, xstatus, xepc, xintstatus and jump to
correct PC according to the CLIC specification.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 117 +++++++++++++++++++++++++++++++++++---
2 files changed, 111 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 494e41edc9..d8378d2384 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -557,6 +557,7 @@
#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16
#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17
+#define RISCV_EXCP_INT_CLIC 0x40000000
#define RISCV_EXCP_INT_FLAG 0x80000000
#define RISCV_EXCP_INT_MASK 0x7fffffff
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 21c54ef561..998d1a2742 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -26,6 +26,10 @@
#include "trace.h"
#include "semihosting/common-semi.h"
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/intc/riscv_clic.h"
+#endif
+
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
@@ -36,6 +40,20 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
}
#ifndef CONFIG_USER_ONLY
+static int riscv_cpu_local_irq_mode_enabled(CPURISCVState *env, int mode)
+{
+ switch (mode) {
+ case PRV_M:
+ return env->priv < PRV_M ||
+ (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE));
+ case PRV_S:
+ return env->priv < PRV_S ||
+ (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
+ default:
+ return false;
+ }
+}
+
static int riscv_cpu_local_irq_pending(CPURISCVState *env)
{
target_ulong irqs;
@@ -90,6 +108,18 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return true;
}
}
+ if (interrupt_request & CPU_INTERRUPT_CLIC) {
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ int mode = (env->exccode >> 12) & 0b11;
+ int enabled = riscv_cpu_local_irq_mode_enabled(env, mode);
+ if (enabled) {
+ cs->exception_index = RISCV_EXCP_INT_CLIC | env->exccode;
+ cs->interrupt_request = cs->interrupt_request & ~CPU_INTERRUPT_CLIC;
+ riscv_cpu_do_interrupt(cs);
+ return true;
+ }
+ }
#endif
return false;
}
@@ -884,6 +914,55 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
#endif
}
+
+#if !defined(CONFIG_USER_ONLY)
+static target_ulong riscv_intr_pc(CPURISCVState *env, target_ulong tvec,
+ target_ulong tvt, bool async, bool clic,
+ int cause, int mode)
+{
+ int mode1 = tvec & 0b11, mode2 = tvec & 0b111111;
+ CPUState *cs = env_cpu(env);
+
+ if (!(async || clic)) {
+ return tvec & ~0b11;
+ }
+ /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
+ switch (mode1) {
+ case 0b00:
+ return tvec & ~0b11;
+ case 0b01:
+ return (tvec & ~0b11) + cause * 4;
+ default:
+ if (env->clic && (mode2 == 0b000011)) {
+ /* Non-vectored, clicintattr[i].shv = 0 || cliccfg.nvbits = 0 */
+ if (!riscv_clic_shv_interrupt(env->clic, mode, cs->cpu_index,
+ cause)) {
+ /* NBASE = mtvec[XLEN-1:6]<<6 */
+ return tvec & ~0b111111;
+ } else {
+ /*
+ * pc := M[TBASE + XLEN/8 * exccode)] & ~1,
+ * TBASE = mtvt[XLEN-1:6]<<6
+ */
+ int size = TARGET_LONG_BITS / 8;
+ target_ulong tbase = (tvt & ~0b111111) + size * cause;
+ void *host = tlb_vaddr_to_host(env, tbase, MMU_DATA_LOAD, mode);
+ if (host != NULL) {
+ target_ulong new_pc = ldn_p(host, size);
+ if (tlb_vaddr_to_host(env, new_pc, MMU_INST_FETCH, mode)) {
+ return new_pc;
+ }
+ }
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "CLIC: load trap handler error!\n");
+ exit(1);
+ }
+ }
+ g_assert_not_reached();
+ }
+}
+#endif
+
/*
* Handle Traps
*
@@ -898,11 +977,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
CPURISCVState *env = &cpu->env;
bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env);
uint64_t s;
+ int mode, level;
/* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
* so we mask off the MSB and separate into trap type and cause.
*/
bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
+ bool clic = !!(cs->exception_index & RISCV_EXCP_INT_CLIC);
target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
target_ulong deleg = async ? env->mideleg : env->medeleg;
bool write_tval = false;
@@ -958,6 +1039,28 @@ void riscv_cpu_do_interrupt(CPUState *cs)
}
}
+ if (clic) {
+ mode = (cause >> 12) & 3;
+ level = (cause >> 14) & 0xff;
+ cause &= 0xfff;
+ cause |= get_field(env->mstatus, MSTATUS_MPP) << 28;
+ switch (mode) {
+ case PRV_M:
+ cause |= get_field(env->mintstatus, MINTSTATUS_MIL) << 16;
+ cause |= get_field(env->mstatus, MSTATUS_MIE) << 27;
+ env->mintstatus = set_field(env->mintstatus, MINTSTATUS_MIL, level);
+ break;
+ case PRV_S:
+ cause |= get_field(env->mintstatus, MINTSTATUS_SIL) << 16;
+ cause |= get_field(env->mstatus, MSTATUS_SPIE) << 27;
+ env->mintstatus = set_field(env->mintstatus, MINTSTATUS_SIL, level);
+ break;
+ }
+ } else {
+ mode = env->priv <= PRV_S &&
+ cause < TARGET_LONG_BITS && ((deleg >> cause) & 1) ? PRV_S : PRV_M;
+ }
+
trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
riscv_cpu_get_trap_name(cause, async));
@@ -967,8 +1070,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
__func__, env->mhartid, async, cause, env->pc, tval,
riscv_cpu_get_trap_name(cause, async));
- if (env->priv <= PRV_S &&
- cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
+ if (mode == PRV_S) {
/* handle the trap in S-mode */
if (riscv_has_ext(env, RVH)) {
target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
@@ -1021,12 +1123,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
- env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
+ env->scause = cause | ((target_ulong)(async | clic) <<
+ (TARGET_LONG_BITS - 1));
env->sepc = env->pc;
env->sbadaddr = tval;
env->htval = htval;
- env->pc = (env->stvec >> 2 << 2) +
- ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
+ env->pc = riscv_intr_pc(env, env->stvec, env->stvt, async,
+ clic & 0xfff, cause, PRV_S);
riscv_cpu_set_mode(env, PRV_S);
} else {
/* handle the trap in M-mode */
@@ -1056,8 +1159,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->mepc = env->pc;
env->mbadaddr = tval;
env->mtval2 = mtval2;
- env->pc = (env->mtvec >> 2 << 2) +
- ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
+ env->pc = riscv_intr_pc(env, env->mtvec, env->mtvt, async,
+ clic, cause & 0xfff, PRV_M);
riscv_cpu_set_mode(env, PRV_M);
}
--
2.25.1
next prev parent reply other threads:[~2021-04-09 7:53 UTC|newest]
Thread overview: 162+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-09 7:48 [RFC PATCH 00/11] RISC-V: support clic v0.9 specification LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-04-09 7:48 ` [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-04-19 23:23 ` Alistair Francis
2021-04-19 23:23 ` Alistair Francis
2021-04-20 0:49 ` LIU Zhiwei
2021-04-20 0:49 ` LIU Zhiwei
2021-07-01 8:45 ` Frank Chang
2021-07-01 8:45 ` Frank Chang
2021-07-01 9:38 ` LIU Zhiwei
2021-07-01 9:38 ` LIU Zhiwei
2021-07-02 5:38 ` Alistair Francis
2021-07-02 5:38 ` Alistair Francis
2021-07-02 6:09 ` LIU Zhiwei
2021-07-02 6:09 ` LIU Zhiwei
2021-07-02 7:16 ` Alistair Francis
2021-07-02 7:16 ` Alistair Francis
2021-09-28 8:10 ` Frank Chang
2021-09-28 8:10 ` Frank Chang
2021-09-29 3:55 ` Alistair Francis
2021-09-29 3:55 ` Alistair Francis
2021-04-09 7:48 ` [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-26 17:23 ` Frank Chang
2021-06-26 17:23 ` Frank Chang
2021-06-27 8:23 ` Frank Chang
2021-06-27 8:23 ` Frank Chang
2021-04-09 7:48 ` [RFC PATCH 03/11] hw/intc: Add CLIC device LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-04-19 23:25 ` Alistair Francis
2021-04-19 23:25 ` Alistair Francis
2021-04-20 0:57 ` LIU Zhiwei
2021-04-20 0:57 ` LIU Zhiwei
2021-04-22 0:16 ` Alistair Francis
2021-04-22 0:16 ` Alistair Francis
2021-06-13 10:10 ` Frank Chang
2021-06-13 10:10 ` Frank Chang
2021-06-16 2:56 ` LIU Zhiwei
2021-06-16 2:56 ` LIU Zhiwei
2021-06-26 12:56 ` Frank Chang
2021-06-26 12:56 ` Frank Chang
2021-06-28 7:15 ` LIU Zhiwei
2021-06-28 7:15 ` LIU Zhiwei
2021-06-28 7:23 ` Frank Chang
2021-06-28 7:23 ` Frank Chang
2021-06-28 7:39 ` LIU Zhiwei
2021-06-28 7:39 ` LIU Zhiwei
2021-06-28 7:49 ` Frank Chang
2021-06-28 7:49 ` Frank Chang
2021-06-28 8:01 ` LIU Zhiwei
2021-06-28 8:01 ` LIU Zhiwei
2021-06-28 8:07 ` Frank Chang
2021-06-28 8:07 ` Frank Chang
2021-06-28 8:11 ` LIU Zhiwei
2021-06-28 8:11 ` LIU Zhiwei
2021-06-28 8:19 ` Frank Chang
2021-06-28 8:19 ` Frank Chang
2021-06-28 8:43 ` LIU Zhiwei
2021-06-28 8:43 ` LIU Zhiwei
2021-06-28 9:11 ` Frank Chang
2021-06-28 9:11 ` Frank Chang
2021-06-26 15:03 ` Frank Chang
2021-06-26 15:03 ` Frank Chang
2021-06-26 15:26 ` Frank Chang
2021-06-26 15:26 ` Frank Chang
2021-06-29 2:52 ` LIU Zhiwei
2021-06-29 2:52 ` LIU Zhiwei
2021-06-29 2:43 ` LIU Zhiwei
2021-06-29 2:43 ` LIU Zhiwei
2021-06-30 5:37 ` Frank Chang
2021-06-30 5:37 ` Frank Chang
2021-06-26 15:20 ` Frank Chang
2021-06-26 15:20 ` Frank Chang
2021-06-29 2:50 ` LIU Zhiwei
2021-06-29 2:50 ` LIU Zhiwei
2021-06-26 17:15 ` Frank Chang
2021-06-26 17:15 ` Frank Chang
2021-06-26 17:19 ` Frank Chang
2021-06-26 17:19 ` Frank Chang
2021-06-28 10:16 ` Frank Chang
2021-06-28 10:16 ` Frank Chang
2021-06-28 12:56 ` LIU Zhiwei
2021-06-28 12:56 ` LIU Zhiwei
2021-06-28 14:30 ` Frank Chang
2021-06-28 14:30 ` Frank Chang
2021-06-28 21:36 ` LIU Zhiwei
2021-06-28 21:36 ` LIU Zhiwei
2021-06-28 10:24 ` Frank Chang
2021-06-28 10:24 ` Frank Chang
2021-06-28 10:48 ` LIU Zhiwei
2021-06-28 10:48 ` LIU Zhiwei
2021-07-13 6:53 ` Frank Chang
2021-07-13 6:53 ` Frank Chang
2021-07-13 6:57 ` Frank Chang
2021-07-13 6:57 ` Frank Chang
2021-04-09 7:48 ` [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-27 6:50 ` Frank Chang
2021-06-27 6:50 ` Frank Chang
2021-04-09 7:48 ` [RFC PATCH 05/11] target/riscv: Update CSR xip " LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-27 6:45 ` Frank Chang
2021-06-27 6:45 ` Frank Chang
2021-04-09 7:48 ` [RFC PATCH 06/11] target/riscv: Update CSR xtvec " LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-27 8:59 ` Frank Chang
2021-06-27 8:59 ` Frank Chang
2021-07-10 15:04 ` Frank Chang
2021-07-10 15:04 ` Frank Chang
2021-04-09 7:48 ` [RFC PATCH 07/11] target/riscv: Update CSR xtvt " LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-27 8:33 ` Frank Chang
2021-06-27 8:33 ` Frank Chang
2021-04-09 7:48 ` [RFC PATCH 08/11] target/riscv: Update CSR xnxti " LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-11 8:15 ` Frank Chang
2021-06-11 8:15 ` Frank Chang
2021-06-11 8:30 ` LIU Zhiwei
2021-06-11 8:30 ` LIU Zhiwei
2021-06-11 8:42 ` Frank Chang
2021-06-11 8:42 ` Frank Chang
2021-06-11 8:56 ` LIU Zhiwei
2021-06-11 8:56 ` LIU Zhiwei
2021-06-11 9:07 ` Frank Chang
2021-06-11 9:07 ` Frank Chang
2021-06-11 9:26 ` LIU Zhiwei
2021-06-11 9:26 ` LIU Zhiwei
2021-06-15 7:45 ` Alistair Francis
2021-06-15 7:45 ` Alistair Francis
2021-06-27 10:07 ` Frank Chang
2021-06-27 10:07 ` Frank Chang
2021-07-10 14:59 ` Frank Chang
2021-07-10 14:59 ` Frank Chang
2021-04-09 7:48 ` [RFC PATCH 09/11] target/riscv: Update CSR mclicbase " LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-26 15:31 ` Frank Chang
2021-06-26 15:31 ` Frank Chang
2021-06-29 2:54 ` LIU Zhiwei
2021-06-29 2:54 ` LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei [this message]
2021-04-09 7:48 ` [RFC PATCH 10/11] target/riscv: Update interrupt handling " LIU Zhiwei
2021-06-27 15:39 ` Frank Chang
2021-06-27 15:39 ` Frank Chang
2021-04-09 7:48 ` [RFC PATCH 11/11] target/riscv: Update interrupt return " LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-27 12:08 ` Frank Chang
2021-06-27 12:08 ` Frank Chang
2021-07-13 7:15 ` Frank Chang
2021-07-13 7:15 ` Frank Chang
2021-04-19 23:30 ` [RFC PATCH 00/11] RISC-V: support clic v0.9 specification Alistair Francis
2021-04-19 23:30 ` Alistair Francis
2021-04-20 1:44 ` LIU Zhiwei
2021-04-20 1:44 ` LIU Zhiwei
2021-04-20 6:26 ` Alistair Francis
2021-04-20 6:26 ` Alistair Francis
2021-04-20 7:20 ` LIU Zhiwei
2021-04-20 7:20 ` LIU Zhiwei
2021-04-22 0:21 ` Alistair Francis
2021-04-22 0:21 ` Alistair Francis
2021-06-27 15:55 ` Frank Chang
2021-06-27 15:55 ` Frank Chang
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