From: Frank Chang <frank.chang@sifive.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
wxy194768@alibaba-inc.com
Subject: Re: [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode
Date: Sun, 27 Jun 2021 14:50:51 +0800 [thread overview]
Message-ID: <CANzO1D0Tx0oB=t8aLhFN95Kq00OP-=wv5mPOYesof_dG6Bap-w@mail.gmail.com> (raw)
In-Reply-To: <20210409074857.166082-5-zhiwei_liu@c-sky.com>
[-- Attachment #1: Type: text/plain, Size: 2733 bytes --]
LIU Zhiwei <zhiwei_liu@c-sky.com> 於 2021年4月9日 週五 下午3:51寫道：
> The xie CSR appears hardwired to zero in CLIC mode, replaced by separate
> memory-mapped interrupt enables (clicintie[i]). Writes to xie will be
> ignored and will not trap (i.e., no access faults).
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/csr.c | 19 ++++++++++++++++---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 4c31364967..74bc7a08aa 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -23,6 +23,10 @@
> #include "qemu/main-loop.h"
> #include "exec/exec-all.h"
>
> +#if !defined(CONFIG_USER_ONLY)
> +#include "hw/intc/riscv_clic.h"
> +#endif
> +
> /* CSR function table public API */
> void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
> {
> @@ -611,13 +615,17 @@ static int write_mideleg(CPURISCVState *env, int
> csrno, target_ulong val)
>
> static int read_mie(CPURISCVState *env, int csrno, target_ulong *val)
> {
> - *val = env->mie;
> + /* The xie CSR appears hardwired to zero in CLIC mode, (Section 4.3)
> */
> + *val = riscv_clic_is_clic_mode(env) ? 0 : env->mie;
> return 0;
> }
>
> static int write_mie(CPURISCVState *env, int csrno, target_ulong val)
> {
> - env->mie = (env->mie & ~all_ints) | (val & all_ints);
> + /* Writes to xie will be ignored and will not trap. (Section 4.3) */
> + if (!riscv_clic_is_clic_mode(env)) {
> + env->mie = (env->mie & ~all_ints) | (val & all_ints);
> + }
> return 0;
> }
>
> @@ -785,7 +793,8 @@ static int read_sie(CPURISCVState *env, int csrno,
> target_ulong *val)
> if (riscv_cpu_virt_enabled(env)) {
> read_vsie(env, CSR_VSIE, val);
> } else {
> - *val = env->mie & env->mideleg;
> + /* The xie CSR appears hardwired to zero in CLIC mode. (Section
> 4.3) */
> + *val = riscv_clic_is_clic_mode(env) ? 0 : env->mie & env->mideleg;
> }
> return 0;
> }
> @@ -805,6 +814,10 @@ static int write_sie(CPURISCVState *env, int csrno,
> target_ulong val)
> } else {
> target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
> (val & S_MODE_INTERRUPTS);
> + /* Writes to xie will be ignored and will not trap. (Section 4.3)
> */
> + if (riscv_clic_is_clic_mode(env)) {
> + return 0;
>
+ }
>
Minor:
This one can be omitted as write_sie() will eventually call write_mie().
Anyway,
Reviewed-by: Frank Chang <frank.chang@sifive.com>
> write_mie(env, CSR_MIE, newval);
> }
>
> --
> 2.25.1
>
>
>
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WARNING: multiple messages have this Message-ID (diff)
From: Frank Chang <frank.chang@sifive.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
wxy194768@alibaba-inc.com
Subject: Re: [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode
Date: Sun, 27 Jun 2021 14:50:51 +0800 [thread overview]
Message-ID: <CANzO1D0Tx0oB=t8aLhFN95Kq00OP-=wv5mPOYesof_dG6Bap-w@mail.gmail.com> (raw)
In-Reply-To: <20210409074857.166082-5-zhiwei_liu@c-sky.com>
[-- Attachment #1: Type: text/plain, Size: 2733 bytes --]
LIU Zhiwei <zhiwei_liu@c-sky.com> 於 2021年4月9日 週五 下午3:51寫道：
> The xie CSR appears hardwired to zero in CLIC mode, replaced by separate
> memory-mapped interrupt enables (clicintie[i]). Writes to xie will be
> ignored and will not trap (i.e., no access faults).
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/csr.c | 19 ++++++++++++++++---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 4c31364967..74bc7a08aa 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -23,6 +23,10 @@
> #include "qemu/main-loop.h"
> #include "exec/exec-all.h"
>
> +#if !defined(CONFIG_USER_ONLY)
> +#include "hw/intc/riscv_clic.h"
> +#endif
> +
> /* CSR function table public API */
> void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
> {
> @@ -611,13 +615,17 @@ static int write_mideleg(CPURISCVState *env, int
> csrno, target_ulong val)
>
> static int read_mie(CPURISCVState *env, int csrno, target_ulong *val)
> {
> - *val = env->mie;
> + /* The xie CSR appears hardwired to zero in CLIC mode, (Section 4.3)
> */
> + *val = riscv_clic_is_clic_mode(env) ? 0 : env->mie;
> return 0;
> }
>
> static int write_mie(CPURISCVState *env, int csrno, target_ulong val)
> {
> - env->mie = (env->mie & ~all_ints) | (val & all_ints);
> + /* Writes to xie will be ignored and will not trap. (Section 4.3) */
> + if (!riscv_clic_is_clic_mode(env)) {
> + env->mie = (env->mie & ~all_ints) | (val & all_ints);
> + }
> return 0;
> }
>
> @@ -785,7 +793,8 @@ static int read_sie(CPURISCVState *env, int csrno,
> target_ulong *val)
> if (riscv_cpu_virt_enabled(env)) {
> read_vsie(env, CSR_VSIE, val);
> } else {
> - *val = env->mie & env->mideleg;
> + /* The xie CSR appears hardwired to zero in CLIC mode. (Section
> 4.3) */
> + *val = riscv_clic_is_clic_mode(env) ? 0 : env->mie & env->mideleg;
> }
> return 0;
> }
> @@ -805,6 +814,10 @@ static int write_sie(CPURISCVState *env, int csrno,
> target_ulong val)
> } else {
> target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
> (val & S_MODE_INTERRUPTS);
> + /* Writes to xie will be ignored and will not trap. (Section 4.3)
> */
> + if (riscv_clic_is_clic_mode(env)) {
> + return 0;
>
+ }
>
Minor:
This one can be omitted as write_sie() will eventually call write_mie().
Anyway,
Reviewed-by: Frank Chang <frank.chang@sifive.com>
> write_mie(env, CSR_MIE, newval);
> }
>
> --
> 2.25.1
>
>
>
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next prev parent reply other threads:[~2021-06-27 6:52 UTC|newest]
Thread overview: 162+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-09 7:48 [RFC PATCH 00/11] RISC-V: support clic v0.9 specification LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-04-09 7:48 ` [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-04-19 23:23 ` Alistair Francis
2021-04-19 23:23 ` Alistair Francis
2021-04-20 0:49 ` LIU Zhiwei
2021-04-20 0:49 ` LIU Zhiwei
2021-07-01 8:45 ` Frank Chang
2021-07-01 8:45 ` Frank Chang
2021-07-01 9:38 ` LIU Zhiwei
2021-07-01 9:38 ` LIU Zhiwei
2021-07-02 5:38 ` Alistair Francis
2021-07-02 5:38 ` Alistair Francis
2021-07-02 6:09 ` LIU Zhiwei
2021-07-02 6:09 ` LIU Zhiwei
2021-07-02 7:16 ` Alistair Francis
2021-07-02 7:16 ` Alistair Francis
2021-09-28 8:10 ` Frank Chang
2021-09-28 8:10 ` Frank Chang
2021-09-29 3:55 ` Alistair Francis
2021-09-29 3:55 ` Alistair Francis
2021-04-09 7:48 ` [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-26 17:23 ` Frank Chang
2021-06-26 17:23 ` Frank Chang
2021-06-27 8:23 ` Frank Chang
2021-06-27 8:23 ` Frank Chang
2021-04-09 7:48 ` [RFC PATCH 03/11] hw/intc: Add CLIC device LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-04-19 23:25 ` Alistair Francis
2021-04-19 23:25 ` Alistair Francis
2021-04-20 0:57 ` LIU Zhiwei
2021-04-20 0:57 ` LIU Zhiwei
2021-04-22 0:16 ` Alistair Francis
2021-04-22 0:16 ` Alistair Francis
2021-06-13 10:10 ` Frank Chang
2021-06-13 10:10 ` Frank Chang
2021-06-16 2:56 ` LIU Zhiwei
2021-06-16 2:56 ` LIU Zhiwei
2021-06-26 12:56 ` Frank Chang
2021-06-26 12:56 ` Frank Chang
2021-06-28 7:15 ` LIU Zhiwei
2021-06-28 7:15 ` LIU Zhiwei
2021-06-28 7:23 ` Frank Chang
2021-06-28 7:23 ` Frank Chang
2021-06-28 7:39 ` LIU Zhiwei
2021-06-28 7:39 ` LIU Zhiwei
2021-06-28 7:49 ` Frank Chang
2021-06-28 7:49 ` Frank Chang
2021-06-28 8:01 ` LIU Zhiwei
2021-06-28 8:01 ` LIU Zhiwei
2021-06-28 8:07 ` Frank Chang
2021-06-28 8:07 ` Frank Chang
2021-06-28 8:11 ` LIU Zhiwei
2021-06-28 8:11 ` LIU Zhiwei
2021-06-28 8:19 ` Frank Chang
2021-06-28 8:19 ` Frank Chang
2021-06-28 8:43 ` LIU Zhiwei
2021-06-28 8:43 ` LIU Zhiwei
2021-06-28 9:11 ` Frank Chang
2021-06-28 9:11 ` Frank Chang
2021-06-26 15:03 ` Frank Chang
2021-06-26 15:03 ` Frank Chang
2021-06-26 15:26 ` Frank Chang
2021-06-26 15:26 ` Frank Chang
2021-06-29 2:52 ` LIU Zhiwei
2021-06-29 2:52 ` LIU Zhiwei
2021-06-29 2:43 ` LIU Zhiwei
2021-06-29 2:43 ` LIU Zhiwei
2021-06-30 5:37 ` Frank Chang
2021-06-30 5:37 ` Frank Chang
2021-06-26 15:20 ` Frank Chang
2021-06-26 15:20 ` Frank Chang
2021-06-29 2:50 ` LIU Zhiwei
2021-06-29 2:50 ` LIU Zhiwei
2021-06-26 17:15 ` Frank Chang
2021-06-26 17:15 ` Frank Chang
2021-06-26 17:19 ` Frank Chang
2021-06-26 17:19 ` Frank Chang
2021-06-28 10:16 ` Frank Chang
2021-06-28 10:16 ` Frank Chang
2021-06-28 12:56 ` LIU Zhiwei
2021-06-28 12:56 ` LIU Zhiwei
2021-06-28 14:30 ` Frank Chang
2021-06-28 14:30 ` Frank Chang
2021-06-28 21:36 ` LIU Zhiwei
2021-06-28 21:36 ` LIU Zhiwei
2021-06-28 10:24 ` Frank Chang
2021-06-28 10:24 ` Frank Chang
2021-06-28 10:48 ` LIU Zhiwei
2021-06-28 10:48 ` LIU Zhiwei
2021-07-13 6:53 ` Frank Chang
2021-07-13 6:53 ` Frank Chang
2021-07-13 6:57 ` Frank Chang
2021-07-13 6:57 ` Frank Chang
2021-04-09 7:48 ` [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-27 6:50 ` Frank Chang [this message]
2021-06-27 6:50 ` Frank Chang
2021-04-09 7:48 ` [RFC PATCH 05/11] target/riscv: Update CSR xip " LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-27 6:45 ` Frank Chang
2021-06-27 6:45 ` Frank Chang
2021-04-09 7:48 ` [RFC PATCH 06/11] target/riscv: Update CSR xtvec " LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-27 8:59 ` Frank Chang
2021-06-27 8:59 ` Frank Chang
2021-07-10 15:04 ` Frank Chang
2021-07-10 15:04 ` Frank Chang
2021-04-09 7:48 ` [RFC PATCH 07/11] target/riscv: Update CSR xtvt " LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-27 8:33 ` Frank Chang
2021-06-27 8:33 ` Frank Chang
2021-04-09 7:48 ` [RFC PATCH 08/11] target/riscv: Update CSR xnxti " LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-11 8:15 ` Frank Chang
2021-06-11 8:15 ` Frank Chang
2021-06-11 8:30 ` LIU Zhiwei
2021-06-11 8:30 ` LIU Zhiwei
2021-06-11 8:42 ` Frank Chang
2021-06-11 8:42 ` Frank Chang
2021-06-11 8:56 ` LIU Zhiwei
2021-06-11 8:56 ` LIU Zhiwei
2021-06-11 9:07 ` Frank Chang
2021-06-11 9:07 ` Frank Chang
2021-06-11 9:26 ` LIU Zhiwei
2021-06-11 9:26 ` LIU Zhiwei
2021-06-15 7:45 ` Alistair Francis
2021-06-15 7:45 ` Alistair Francis
2021-06-27 10:07 ` Frank Chang
2021-06-27 10:07 ` Frank Chang
2021-07-10 14:59 ` Frank Chang
2021-07-10 14:59 ` Frank Chang
2021-04-09 7:48 ` [RFC PATCH 09/11] target/riscv: Update CSR mclicbase " LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-26 15:31 ` Frank Chang
2021-06-26 15:31 ` Frank Chang
2021-06-29 2:54 ` LIU Zhiwei
2021-06-29 2:54 ` LIU Zhiwei
2021-04-09 7:48 ` [RFC PATCH 10/11] target/riscv: Update interrupt handling " LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-27 15:39 ` Frank Chang
2021-06-27 15:39 ` Frank Chang
2021-04-09 7:48 ` [RFC PATCH 11/11] target/riscv: Update interrupt return " LIU Zhiwei
2021-04-09 7:48 ` LIU Zhiwei
2021-06-27 12:08 ` Frank Chang
2021-06-27 12:08 ` Frank Chang
2021-07-13 7:15 ` Frank Chang
2021-07-13 7:15 ` Frank Chang
2021-04-19 23:30 ` [RFC PATCH 00/11] RISC-V: support clic v0.9 specification Alistair Francis
2021-04-19 23:30 ` Alistair Francis
2021-04-20 1:44 ` LIU Zhiwei
2021-04-20 1:44 ` LIU Zhiwei
2021-04-20 6:26 ` Alistair Francis
2021-04-20 6:26 ` Alistair Francis
2021-04-20 7:20 ` LIU Zhiwei
2021-04-20 7:20 ` LIU Zhiwei
2021-04-22 0:21 ` Alistair Francis
2021-04-22 0:21 ` Alistair Francis
2021-06-27 15:55 ` Frank Chang
2021-06-27 15:55 ` Frank Chang
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