From: Dave Jiang <dave.jiang@intel.com>
To: linux-cxl@vger.kernel.org
Cc: dan.j.williams@intel.com, ira.weiny@intel.com,
vishal.l.verma@intel.com, alison.schofield@intel.com,
Jonathan.Cameron@huawei.com, dave@stgolabs.net
Subject: [PATCH v7 5/5] cxl: Add checks to access_coordinate calculation to fail missing data
Date: Wed, 3 Apr 2024 08:47:16 -0700 [thread overview]
Message-ID: <20240403154844.3403859-6-dave.jiang@intel.com> (raw)
In-Reply-To: <20240403154844.3403859-1-dave.jiang@intel.com>
Jonathan noted that when the coordinates for host bridge and switches
can be 0s if no actual data are retrieved and the calculation continues.
The resulting number would be inaccurate. Add checks to ensure that the
calculation would complete only if the numbers are valid.
While not seen in the wild, issue may show up with a BIOS that reported
CXL root ports via Generic Ports (via a PCI handle in the SRAT entry).
Fixes: 14a6960b3e92 ("cxl: Add helper function that calculate performance data for downstream ports")
Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/core/port.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 801c4018a1dd..762783bb091a 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -2141,6 +2141,18 @@ static void add_latency(struct access_coordinate *c, long latency)
}
}
+static bool coordinates_valid(struct access_coordinate *c)
+{
+ for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) {
+ if (c[i].read_bandwidth && c[i].write_bandwidth &&
+ c[i].read_latency && c[i].write_latency)
+ continue;
+ return false;
+ }
+
+ return true;
+}
+
static void set_min_bandwidth(struct access_coordinate *c, unsigned int bw)
{
for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) {
@@ -2206,13 +2218,18 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,
* There's no valid access_coordinate for a root port since RPs do not
* have CDAT and therefore needs to be skipped.
*/
- if (!is_cxl_root)
+ if (!is_cxl_root) {
+ if (!coordinates_valid(dport->coord))
+ return -EINVAL;
cxl_coordinates_combine(c, c, dport->coord);
+ }
add_latency(c, dport->link_latency);
} while (!is_cxl_root);
dport = iter->parent_dport;
/* Retrieve HB coords */
+ if (!coordinates_valid(dport->coord))
+ return -EINVAL;
cxl_coordinates_combine(c, c, dport->coord);
/* Get the calculated PCI paths bandwidth */
--
2.44.0
next prev parent reply other threads:[~2024-04-03 15:48 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-03 15:47 [PATCH v7 0/5] cxl: access_coordinate validity fixes for 6.9 Dave Jiang
2024-04-03 15:47 ` [PATCH v7 1/5] cxl: Remove checking of iter in cxl_endpoint_get_perf_coordinates() Dave Jiang
2024-04-26 19:10 ` Robert Richter
2024-04-26 20:13 ` Dave Jiang
2024-04-03 15:47 ` [PATCH v7 2/5] cxl: Fix retrieving of access_coordinates in PCIe path Dave Jiang
2024-04-05 13:32 ` Jonathan Cameron
2024-04-05 22:24 ` Dan Williams
2024-04-03 15:47 ` [PATCH v7 3/5] cxl: Fix incorrect region perf data calculation Dave Jiang
2024-04-05 13:48 ` Jonathan Cameron
2024-04-05 22:34 ` Dan Williams
2024-04-08 9:54 ` Jonathan Cameron
2024-04-03 15:47 ` [PATCH v7 4/5] cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coord Dave Jiang
2024-04-03 15:47 ` Dave Jiang [this message]
2024-04-05 22:36 ` [PATCH v7 5/5] cxl: Add checks to access_coordinate calculation to fail missing data Dan Williams
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