From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <dan.j.williams@intel.com>,
<ira.weiny@intel.com>, <vishal.l.verma@intel.com>,
<alison.schofield@intel.com>, <dave@stgolabs.net>
Subject: Re: [PATCH v7 2/5] cxl: Fix retrieving of access_coordinates in PCIe path
Date: Fri, 5 Apr 2024 14:32:42 +0100 [thread overview]
Message-ID: <20240405143242.0000363a@Huawei.com> (raw)
In-Reply-To: <20240403154844.3403859-3-dave.jiang@intel.com>
On Wed, 3 Apr 2024 08:47:13 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> Current loop in cxl_endpoint_get_perf_coordinates() incorrectly assumes
> the Root Port (RP) dport is the one with generic port access_coordinate.
> However those coordinates are one level up in the Host Bridge (HB).
> Current code causes the computation code to pick up 0s as the coordinates
> and cause minimal bandwidth to result in 0.
>
> Add check to skip RP when combining coordinates.
>
> Fixes: 4d59ba915318 ("cxl: Fix retrieving of access_coordinates in PCIe path")
> Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
I've only tested this with direct connect, but can't see why it wouldn't work
with switches in the path. So
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core/port.c | 35 ++++++++++++++++++++++-------------
> 1 file changed, 22 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 6cbde50a742b..7aadcec4fc64 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -2165,6 +2165,11 @@ int cxl_hb_get_perf_coordinates(struct cxl_port *port,
> return 0;
> }
>
> +static bool parent_port_is_cxl_root(struct cxl_port *port)
> +{
> + return is_cxl_root(to_cxl_port(port->dev.parent));
> +}
> +
> /**
> * cxl_endpoint_get_perf_coordinates - Retrieve performance numbers stored in dports
> * of CXL path
> @@ -2184,27 +2189,31 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,
> struct cxl_dport *dport;
> struct pci_dev *pdev;
> unsigned int bw;
> + bool is_cxl_root;
>
> if (!is_cxl_endpoint(port))
> return -EINVAL;
>
> - dport = iter->parent_dport;
> -
> /*
> - * Exit the loop when the parent port of the current port is cxl root.
> - * The iterative loop starts at the endpoint and gathers the
> - * latency of the CXL link from the current iter to the next downstream
> - * port each iteration. If the parent is cxl root then there is
> - * nothing to gather.
> + * Exit the loop when the parent port of the current iter port is cxl
> + * root. The iterative loop starts at the endpoint and gathers the
> + * latency of the CXL link from the current device/port to the connected
> + * downstream port each iteration.
> */
> - while (!is_cxl_root(to_cxl_port(iter->dev.parent))) {
> - cxl_coordinates_combine(&c, &c, &dport->sw_coord);
> + do {
> + dport = iter->parent_dport;
> + iter = to_cxl_port(iter->dev.parent);
> + is_cxl_root = parent_port_is_cxl_root(iter);
> +
> + /*
> + * There's no valid access_coordinate for a root port since RPs do not
> + * have CDAT and therefore needs to be skipped.
> + */
> + if (!is_cxl_root)
> + cxl_coordinates_combine(&c, &c, &dport->sw_coord);
> c.write_latency += dport->link_latency;
> c.read_latency += dport->link_latency;
> -
> - iter = to_cxl_port(iter->dev.parent);
> - dport = iter->parent_dport;
> - }
> + } while (!is_cxl_root);
>
> /* Get the calculated PCI paths bandwidth */
> pdev = to_pci_dev(port->uport_dev->parent);
next prev parent reply other threads:[~2024-04-05 13:32 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-03 15:47 [PATCH v7 0/5] cxl: access_coordinate validity fixes for 6.9 Dave Jiang
2024-04-03 15:47 ` [PATCH v7 1/5] cxl: Remove checking of iter in cxl_endpoint_get_perf_coordinates() Dave Jiang
2024-04-26 19:10 ` Robert Richter
2024-04-26 20:13 ` Dave Jiang
2024-04-03 15:47 ` [PATCH v7 2/5] cxl: Fix retrieving of access_coordinates in PCIe path Dave Jiang
2024-04-05 13:32 ` Jonathan Cameron [this message]
2024-04-05 22:24 ` Dan Williams
2024-04-03 15:47 ` [PATCH v7 3/5] cxl: Fix incorrect region perf data calculation Dave Jiang
2024-04-05 13:48 ` Jonathan Cameron
2024-04-05 22:34 ` Dan Williams
2024-04-08 9:54 ` Jonathan Cameron
2024-04-03 15:47 ` [PATCH v7 4/5] cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coord Dave Jiang
2024-04-03 15:47 ` [PATCH v7 5/5] cxl: Add checks to access_coordinate calculation to fail missing data Dave Jiang
2024-04-05 22:36 ` Dan Williams
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240405143242.0000363a@Huawei.com \
--to=jonathan.cameron@huawei.com \
--cc=alison.schofield@intel.com \
--cc=dan.j.williams@intel.com \
--cc=dave.jiang@intel.com \
--cc=dave@stgolabs.net \
--cc=ira.weiny@intel.com \
--cc=linux-cxl@vger.kernel.org \
--cc=vishal.l.verma@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.