From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Matt Roper <matthew.d.roper@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>,
Haridhar Kalvala <haridhar.kalvala@intel.com>,
Clint Taylor <clinton.a.taylor@intel.com>,
Gustavo Sousa <gustavo.sousa@intel.com>,
Dnyaneshar Bhadane <dnyaneshwar.bhadane@intel.com>,
Shekhar Chauhan <shekhar.chauhan@intel.com>,
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Subject: [PATCH v3 09/11] drm/xe/xe2hpg: Add initial GT workarounds
Date: Mon, 8 Apr 2024 22:35:43 +0530 [thread overview]
Message-ID: <20240408170545.3769566-10-balasubramani.vivekanandan@intel.com> (raw)
In-Reply-To: <20240408170545.3769566-1-balasubramani.vivekanandan@intel.com>
From: Haridhar Kalvala <haridhar.kalvala@intel.com>
Add the initial set of Xe2_HPG gt/engine/lrc workarounds.
v2: Removed WA_16020183090 which is no more applicable
Extended WA_18033852989,18034896535 also to xe2hpg
Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Dnyaneshar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +++
drivers/gpu/drm/xe/xe_wa.c | 67 +++++++++++++++++++++++++++-
2 files changed, 70 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index d404f211bc36..0ce79ba19bda 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -74,6 +74,9 @@
#define WM_CHICKEN3 XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)
#define HIZ_PLANE_COMPRESSION_DIS REG_BIT(10)
+#define CHICKEN_RASTER_1 XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED)
+#define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8)
+
#define CHICKEN_RASTER_2 XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED)
#define TBIMR_FAST_CLIP REG_BIT(5)
@@ -355,6 +358,7 @@
#define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
#define ROW_CHICKEN3 XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED)
+#define XE2_EUPEND_CHK_FLUSH_DIS REG_BIT(14)
#define DIS_FIX_EOT1_FLUSH REG_BIT(9)
#define TDL_TSL_CHICKEN XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED)
@@ -385,6 +389,7 @@
#define LSC_CHICKEN_BIT_0 XE_REG_MCR(0xe7c8)
#define DISABLE_D8_D16_COASLESCE REG_BIT(30)
+#define WR_REQ_CHAINING_DIS REG_BIT(26)
#define TGM_WRITE_EOM_FORCE REG_BIT(17)
#define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15)
#define SEQUENTIAL_ACCESS_UPGRADE_DISABLE REG_BIT(13)
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 43fac92e5d20..014d27c126ae 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -429,7 +429,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
},
{ XE_RTP_NAME("18034896535"),
- XE_RTP_RULES(GRAPHICS_VERSION(2004),
+ XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
},
@@ -464,6 +464,55 @@ static const struct xe_rtp_entry_sr engine_was[] = {
XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
},
+
+ /* Xe2_HPG */
+
+ { XE_RTP_NAME("16018712365"),
+ XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
+ XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
+ },
+ { XE_RTP_NAME("16018737384"),
+ XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
+ },
+ { XE_RTP_NAME("14019988906"),
+ XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
+ XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
+ },
+ { XE_RTP_NAME("14019877138"),
+ XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
+ XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
+ },
+ { XE_RTP_NAME("14020338487"),
+ XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
+ },
+ { XE_RTP_NAME("18032247524"),
+ XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
+ XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
+ },
+ { XE_RTP_NAME("14018471104"),
+ XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
+ XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
+ },
+ /*
+ * Although this workaround isn't required for the RCS, disabling these
+ * reports has no impact for our driver or the GuC, so we go ahead and
+ * apply this to all engines for simplicity.
+ */
+ { XE_RTP_NAME("16021639441"),
+ XE_RTP_RULES(GRAPHICS_VERSION(2001)),
+ XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
+ GHWSP_CSB_REPORT_DIS |
+ PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
+ XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+ },
+ { XE_RTP_NAME("14019811474"),
+ XE_RTP_RULES(GRAPHICS_VERSION(2001),
+ FUNC(xe_rtp_match_first_render_or_compute)),
+ XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
+ },
+
{}
};
@@ -585,10 +634,24 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))
},
{ XE_RTP_NAME("18033852989"),
- XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
+ XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
},
+ /* Xe2_HPG */
+ { XE_RTP_NAME("15010599737"),
+ XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
+ XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN))
+ },
+ { XE_RTP_NAME("14019386621"),
+ XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
+ XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
+ },
+ { XE_RTP_NAME("14020756599"),
+ XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
+ XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
+ },
+
{}
};
--
2.25.1
next prev parent reply other threads:[~2024-04-08 17:06 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-08 17:05 [PATCH v3 00/11] Add Battlemage support Balasubramani Vivekanandan
2024-04-08 17:05 ` [PATCH v3 01/11] drm/xe/xe2: Recognize Xe2_HPG IP Balasubramani Vivekanandan
2024-04-08 17:05 ` [PATCH v3 02/11] drm/xe/xe2: Recognize Xe2_HPM IP Balasubramani Vivekanandan
2024-04-08 17:05 ` [PATCH v3 03/11] drm/xe/bmg: Add BMG platform definition Balasubramani Vivekanandan
2024-04-08 19:09 ` Ghimiray, Himal Prasad
2024-04-09 15:46 ` Lucas De Marchi
2024-04-08 17:05 ` [PATCH v3 04/11] drm/xe/bmg: Add BMG mocs table Balasubramani Vivekanandan
2024-04-08 17:05 ` [PATCH v3 05/11] drm/xe/bmg: Program an additional discrete-specific PAT setting Balasubramani Vivekanandan
2024-04-08 19:05 ` Ghimiray, Himal Prasad
2024-04-08 17:05 ` [PATCH v3 06/11] drm/xe/xe2hpg: Determine flat ccs offset for vram Balasubramani Vivekanandan
2024-04-08 21:44 ` Matt Roper
2024-04-08 17:05 ` [PATCH v3 07/11] drm/xe/xe2hpg: Remove extra allocation of CCS pages for dgfx Balasubramani Vivekanandan
2024-04-08 18:57 ` Ghimiray, Himal Prasad
2024-04-08 21:46 ` Matt Roper
2024-04-22 10:15 ` Thomas Hellström
2024-04-08 17:05 ` [PATCH v3 08/11] drm/xe/xe2: Add workaround 18034896535 Balasubramani Vivekanandan
2024-04-26 21:02 ` Lucas De Marchi
2024-04-29 13:51 ` Gustavo Sousa
2024-04-08 17:05 ` Balasubramani Vivekanandan [this message]
2024-04-08 17:05 ` [PATCH v3 10/11] drm/xe/xe2hpg: Introduce performance tuning changes for Xe2_HPG Balasubramani Vivekanandan
2024-04-08 17:05 ` [PATCH v3 11/11] drm/xe/xe2hpm: Add initial set of workarounds Balasubramani Vivekanandan
2024-04-08 18:33 ` ✓ CI.Patch_applied: success for Add Battlemage support (rev3) Patchwork
2024-04-08 18:33 ` ✗ CI.checkpatch: warning " Patchwork
2024-04-08 18:34 ` ✓ CI.KUnit: success " Patchwork
2024-04-08 18:46 ` ✓ CI.Build: " Patchwork
2024-04-08 18:48 ` ✓ CI.Hooks: " Patchwork
2024-04-08 18:50 ` ✓ CI.checksparse: " Patchwork
2024-04-08 19:12 ` ✓ CI.BAT: " Patchwork
2024-04-09 0:34 ` ✓ CI.FULL: " Patchwork
2024-04-09 21:25 ` [PATCH v3 00/11] Add Battlemage support Matt Roper
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