From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Matt Roper <matthew.d.roper@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>,
Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>,
Akshata Jahagirdar <akshata.jahagirdar@intel.com>,
Matthew Auld <matthew.auld@intel.com>,
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Subject: [PATCH v3 06/11] drm/xe/xe2hpg: Determine flat ccs offset for vram
Date: Mon, 8 Apr 2024 22:35:40 +0530 [thread overview]
Message-ID: <20240408170545.3769566-7-balasubramani.vivekanandan@intel.com> (raw)
In-Reply-To: <20240408170545.3769566-1-balasubramani.vivekanandan@intel.com>
From: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
on Xe2 dgfx platform determine the offset using Flat CCS size
bitfield of XE2_FLAT_CCS_BASE_RANGE_[UPPER/LOWER] mcr registers.
Bspec: 68023
v2: function argument tile_size changed from pass by reference to pass
by value
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 ++++
drivers/gpu/drm/xe/xe_mmio.c | 39 ++++++++++++++++++++++++++--
2 files changed, 42 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 6617c86a096b..d404f211bc36 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -69,6 +69,7 @@
#define XEHP_TILE_ADDR_RANGE(_idx) XE_REG_MCR(0x4900 + (_idx) * 4)
#define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910)
+#define XEHP_FLAT_CCS_PTR REG_GENMASK(31, 8)
#define WM_CHICKEN3 XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)
#define HIZ_PLANE_COMPRESSION_DIS REG_BIT(10)
@@ -142,6 +143,10 @@
#define XE2_FLAT_CCS_BASE_RANGE_LOWER XE_REG_MCR(0x8800)
#define XE2_FLAT_CCS_ENABLE REG_BIT(0)
+#define XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK REG_GENMASK(31, 6)
+
+#define XE2_FLAT_CCS_BASE_RANGE_UPPER XE_REG_MCR(0x8804)
+#define XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK REG_GENMASK(7, 0)
#define GSCPSMI_BASE XE_REG(0x880c)
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 5d13fc7cb9d2..d66da1a9f165 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -163,6 +163,42 @@ static int xe_determine_lmem_bar_size(struct xe_device *xe)
return 0;
}
+static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
+{
+ struct xe_device *xe = gt_to_xe(gt);
+ u64 offset;
+ u32 reg;
+
+ if (GRAPHICS_VER(xe) >= 20) {
+ u64 ccs_size = tile_size / 512;
+ u64 offset_hi, offset_lo;
+ u32 nodes, num_enabled;
+
+ reg = xe_mmio_read32(gt, MIRROR_FUSE3);
+ nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg);
+ num_enabled = hweight32(nodes); /* Number of enabled l3 nodes */
+
+ reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER);
+ offset_lo = REG_FIELD_GET(XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK, reg);
+
+ reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_UPPER);
+ offset_hi = REG_FIELD_GET(XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK, reg);
+
+ offset = offset_hi << 32; /* HW view bits 39:32 */
+ offset |= offset_lo << 6; /* HW view bits 31:6 */
+ offset *= num_enabled; /* convert to SW view */
+
+ /* We don't expect any holes */
+ xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(gt, GSMBASE) - ccs_size),
+ "Hole between CCS and GSM.\n");
+ } else {
+ reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
+ offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K;
+ }
+
+ return offset;
+}
+
/**
* xe_mmio_tile_vram_size() - Collect vram size and offset information
* @tile: tile to get info for
@@ -207,8 +243,7 @@ static int xe_mmio_tile_vram_size(struct xe_tile *tile, u64 *vram_size,
/* minus device usage */
if (xe->info.has_flat_ccs) {
- reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
- offset = (u64)REG_FIELD_GET(GENMASK(31, 8), reg) * SZ_64K;
+ offset = get_flat_ccs_offset(gt, *tile_size);
} else {
offset = xe_mmio_read64_2x32(gt, GSMBASE);
}
--
2.25.1
next prev parent reply other threads:[~2024-04-08 17:05 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-08 17:05 [PATCH v3 00/11] Add Battlemage support Balasubramani Vivekanandan
2024-04-08 17:05 ` [PATCH v3 01/11] drm/xe/xe2: Recognize Xe2_HPG IP Balasubramani Vivekanandan
2024-04-08 17:05 ` [PATCH v3 02/11] drm/xe/xe2: Recognize Xe2_HPM IP Balasubramani Vivekanandan
2024-04-08 17:05 ` [PATCH v3 03/11] drm/xe/bmg: Add BMG platform definition Balasubramani Vivekanandan
2024-04-08 19:09 ` Ghimiray, Himal Prasad
2024-04-09 15:46 ` Lucas De Marchi
2024-04-08 17:05 ` [PATCH v3 04/11] drm/xe/bmg: Add BMG mocs table Balasubramani Vivekanandan
2024-04-08 17:05 ` [PATCH v3 05/11] drm/xe/bmg: Program an additional discrete-specific PAT setting Balasubramani Vivekanandan
2024-04-08 19:05 ` Ghimiray, Himal Prasad
2024-04-08 17:05 ` Balasubramani Vivekanandan [this message]
2024-04-08 21:44 ` [PATCH v3 06/11] drm/xe/xe2hpg: Determine flat ccs offset for vram Matt Roper
2024-04-08 17:05 ` [PATCH v3 07/11] drm/xe/xe2hpg: Remove extra allocation of CCS pages for dgfx Balasubramani Vivekanandan
2024-04-08 18:57 ` Ghimiray, Himal Prasad
2024-04-08 21:46 ` Matt Roper
2024-04-22 10:15 ` Thomas Hellström
2024-04-08 17:05 ` [PATCH v3 08/11] drm/xe/xe2: Add workaround 18034896535 Balasubramani Vivekanandan
2024-04-26 21:02 ` Lucas De Marchi
2024-04-29 13:51 ` Gustavo Sousa
2024-04-08 17:05 ` [PATCH v3 09/11] drm/xe/xe2hpg: Add initial GT workarounds Balasubramani Vivekanandan
2024-04-08 17:05 ` [PATCH v3 10/11] drm/xe/xe2hpg: Introduce performance tuning changes for Xe2_HPG Balasubramani Vivekanandan
2024-04-08 17:05 ` [PATCH v3 11/11] drm/xe/xe2hpm: Add initial set of workarounds Balasubramani Vivekanandan
2024-04-08 18:33 ` ✓ CI.Patch_applied: success for Add Battlemage support (rev3) Patchwork
2024-04-08 18:33 ` ✗ CI.checkpatch: warning " Patchwork
2024-04-08 18:34 ` ✓ CI.KUnit: success " Patchwork
2024-04-08 18:46 ` ✓ CI.Build: " Patchwork
2024-04-08 18:48 ` ✓ CI.Hooks: " Patchwork
2024-04-08 18:50 ` ✓ CI.checksparse: " Patchwork
2024-04-08 19:12 ` ✓ CI.BAT: " Patchwork
2024-04-09 0:34 ` ✓ CI.FULL: " Patchwork
2024-04-09 21:25 ` [PATCH v3 00/11] Add Battlemage support Matt Roper
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