From: Conor Dooley <conor@kernel.org> To: Tomasz Jeznach <tjeznach@rivosinc.com> Cc: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <apatel@ventanamicro.com>, Sunil V L <sunilvl@ventanamicro.com>, Nick Kossifidis <mick@ics.forth.gr>, Sebastien Boeuf <seb@rivosinc.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, devicetree@vger.kernel.org, iommu@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux@rivosinc.com Subject: Re: [PATCH v2 1/7] dt-bindings: iommu: riscv: Add bindings for RISC-V IOMMU Date: Thu, 18 Apr 2024 18:04:03 +0100 [thread overview] Message-ID: <20240418-approach-liquefy-04551ddefbc4@spud> (raw) In-Reply-To: <c37cb93e7baa7042a3f82130bf30be6831b558dc.1713456598.git.tjeznach@rivosinc.com> [-- Attachment #1: Type: text/plain, Size: 3123 bytes --] On Thu, Apr 18, 2024 at 09:32:19AM -0700, Tomasz Jeznach wrote: > Add bindings for the RISC-V IOMMU device drivers. > > Co-developed-by: Anup Patel <apatel@ventanamicro.com> > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> > --- > .../bindings/iommu/riscv,iommu.yaml | 149 ++++++++++++++++++ > MAINTAINERS | 7 + > 2 files changed, 156 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iommu/riscv,iommu.yaml > > diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml > new file mode 100644 > index 000000000000..d6522ddd43fa > --- /dev/null > +++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml > @@ -0,0 +1,149 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: RISC-V IOMMU Architecture Implementation > + > +maintainers: > + - Tomasz Jeznach <tjeznach@rivosinc.com> > + > +description: |+ FYI, the + here is probably not needed. > + The RISC-V IOMMU provides memory address translation and isolation for > + input and output devices, supporting per-device translation context, > + shared process address spaces including the ATS and PRI components of > + the PCIe specification, two stage address translation and MSI remapping. > + It supports identical translation table format to the RISC-V address > + translation tables with page level access and protection attributes. > + Hardware uses in-memory command and fault reporting queues with wired > + interrupt or MSI notifications. > + > + Visit https://github.com/riscv-non-isa/riscv-iommu for more details. > + > + For information on assigning RISC-V IOMMU to its peripheral devices, > + see generic IOMMU bindings. > + > +properties: > + # For PCIe IOMMU hardware compatible property should contain the vendor > + # and device ID according to the PCI Bus Binding specification. > + # Since PCI provides built-in identification methods, compatible is not > + # actually required. For non-PCIe hardware implementations 'riscv,iommu' > + # should be specified along with 'reg' property providing MMIO location. I dunno, I'd like to see soc-specific compatibles for implementations of the RISC-V IOMMU. If you need a DT compatible for use in QEMU, I'd suggest doing what was done for the aplic and having a dedicated compatible for that and disallow having "riscv,iommu" in isolation. > + compatible: > + oneOf: > + - items: > + - const: riscv,pci-iommu > + - const: pci1efd,edf1 > + - items: > + - const: pci1efd,edf1 Why are both versions allowed? If the former is more understandable, can't we just go with that? > + - items: > + - const: riscv,iommu Other than the compatible setup I think this is pretty decent though, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org> To: Tomasz Jeznach <tjeznach@rivosinc.com> Cc: Anup Patel <apatel@ventanamicro.com>, devicetree@vger.kernel.org, Conor Dooley <conor+dt@kernel.org>, Albert Ou <aou@eecs.berkeley.edu>, linux@rivosinc.com, Will Deacon <will@kernel.org>, Joerg Roedel <joro@8bytes.org>, linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>, Sebastien Boeuf <seb@rivosinc.com>, iommu@lists.linux.dev, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Nick Kossifidis <mick@ics.forth.gr>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Robin Murphy <robin.murphy@arm.com>, linux-riscv@lists.infradead.org Subject: Re: [PATCH v2 1/7] dt-bindings: iommu: riscv: Add bindings for RISC-V IOMMU Date: Thu, 18 Apr 2024 18:04:03 +0100 [thread overview] Message-ID: <20240418-approach-liquefy-04551ddefbc4@spud> (raw) In-Reply-To: <c37cb93e7baa7042a3f82130bf30be6831b558dc.1713456598.git.tjeznach@rivosinc.com> [-- Attachment #1.1: Type: text/plain, Size: 3123 bytes --] On Thu, Apr 18, 2024 at 09:32:19AM -0700, Tomasz Jeznach wrote: > Add bindings for the RISC-V IOMMU device drivers. > > Co-developed-by: Anup Patel <apatel@ventanamicro.com> > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> > --- > .../bindings/iommu/riscv,iommu.yaml | 149 ++++++++++++++++++ > MAINTAINERS | 7 + > 2 files changed, 156 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iommu/riscv,iommu.yaml > > diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml > new file mode 100644 > index 000000000000..d6522ddd43fa > --- /dev/null > +++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml > @@ -0,0 +1,149 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: RISC-V IOMMU Architecture Implementation > + > +maintainers: > + - Tomasz Jeznach <tjeznach@rivosinc.com> > + > +description: |+ FYI, the + here is probably not needed. > + The RISC-V IOMMU provides memory address translation and isolation for > + input and output devices, supporting per-device translation context, > + shared process address spaces including the ATS and PRI components of > + the PCIe specification, two stage address translation and MSI remapping. > + It supports identical translation table format to the RISC-V address > + translation tables with page level access and protection attributes. > + Hardware uses in-memory command and fault reporting queues with wired > + interrupt or MSI notifications. > + > + Visit https://github.com/riscv-non-isa/riscv-iommu for more details. > + > + For information on assigning RISC-V IOMMU to its peripheral devices, > + see generic IOMMU bindings. > + > +properties: > + # For PCIe IOMMU hardware compatible property should contain the vendor > + # and device ID according to the PCI Bus Binding specification. > + # Since PCI provides built-in identification methods, compatible is not > + # actually required. For non-PCIe hardware implementations 'riscv,iommu' > + # should be specified along with 'reg' property providing MMIO location. I dunno, I'd like to see soc-specific compatibles for implementations of the RISC-V IOMMU. If you need a DT compatible for use in QEMU, I'd suggest doing what was done for the aplic and having a dedicated compatible for that and disallow having "riscv,iommu" in isolation. > + compatible: > + oneOf: > + - items: > + - const: riscv,pci-iommu > + - const: pci1efd,edf1 > + - items: > + - const: pci1efd,edf1 Why are both versions allowed? If the former is more understandable, can't we just go with that? > + - items: > + - const: riscv,iommu Other than the compatible setup I think this is pretty decent though, Conor. [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 161 bytes --] _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-04-18 17:04 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-18 16:32 [PATCH v2 0/7] Linux RISC-V IOMMU Support Tomasz Jeznach 2024-04-18 16:32 ` Tomasz Jeznach 2024-04-18 16:32 ` [PATCH v2 1/7] dt-bindings: iommu: riscv: Add bindings for RISC-V IOMMU Tomasz Jeznach 2024-04-18 16:32 ` Tomasz Jeznach 2024-04-18 17:04 ` Conor Dooley [this message] 2024-04-18 17:04 ` Conor Dooley 2024-04-24 22:37 ` Tomasz Jeznach 2024-04-24 22:37 ` Tomasz Jeznach 2024-04-25 17:11 ` Conor Dooley 2024-04-25 17:11 ` Conor Dooley 2024-04-22 14:04 ` Rob Herring 2024-04-22 14:04 ` Rob Herring 2024-04-18 16:32 ` [PATCH v2 2/7] iommu/riscv: Add RISC-V IOMMU platform device driver Tomasz Jeznach 2024-04-18 16:32 ` Tomasz Jeznach 2024-04-18 21:22 ` Robin Murphy 2024-04-18 21:22 ` Robin Murphy 2024-04-24 21:59 ` Tomasz Jeznach 2024-04-24 21:59 ` Tomasz Jeznach 2024-04-25 11:23 ` Robin Murphy 2024-04-25 11:23 ` Robin Murphy 2024-04-18 16:32 ` [PATCH v2 3/7] iommu/riscv: Add RISC-V IOMMU PCIe " Tomasz Jeznach 2024-04-18 16:32 ` Tomasz Jeznach 2024-04-18 22:07 ` Robin Murphy 2024-04-18 22:07 ` Robin Murphy 2024-04-18 16:32 ` [PATCH v2 4/7] iommu/riscv: Enable IOMMU registration and device probe Tomasz Jeznach 2024-04-18 16:32 ` Tomasz Jeznach 2024-04-18 16:32 ` [PATCH v2 5/7] iommu/riscv: Device directory management Tomasz Jeznach 2024-04-18 16:32 ` Tomasz Jeznach 2024-04-19 12:40 ` Jason Gunthorpe 2024-04-19 12:40 ` Jason Gunthorpe 2024-04-24 23:01 ` Tomasz Jeznach 2024-04-24 23:01 ` Tomasz Jeznach 2024-04-24 23:07 ` Jason Gunthorpe 2024-04-24 23:07 ` Jason Gunthorpe 2024-04-22 5:11 ` Baolu Lu 2024-04-22 5:11 ` Baolu Lu 2024-04-24 23:07 ` Tomasz Jeznach 2024-04-24 23:07 ` Tomasz Jeznach 2024-04-18 16:32 ` [PATCH v2 6/7] iommu/riscv: Command and fault queue support Tomasz Jeznach 2024-04-18 16:32 ` Tomasz Jeznach 2024-04-18 16:32 ` [PATCH v2 7/7] iommu/riscv: Paging domain support Tomasz Jeznach 2024-04-18 16:32 ` Tomasz Jeznach 2024-04-19 12:56 ` Jason Gunthorpe 2024-04-19 12:56 ` Jason Gunthorpe 2024-04-22 7:40 ` Baolu Lu 2024-04-22 7:40 ` Baolu Lu 2024-04-24 23:30 ` Tomasz Jeznach 2024-04-24 23:30 ` Tomasz Jeznach 2024-04-24 23:39 ` Jason Gunthorpe 2024-04-24 23:39 ` Jason Gunthorpe 2024-04-24 23:54 ` Tomasz Jeznach 2024-04-24 23:54 ` Tomasz Jeznach 2024-04-25 0:48 ` Jason Gunthorpe 2024-04-25 0:48 ` Jason Gunthorpe 2024-04-22 5:21 ` Baolu Lu 2024-04-22 5:21 ` Baolu Lu 2024-04-22 19:30 ` Jason Gunthorpe 2024-04-22 19:30 ` Jason Gunthorpe 2024-04-23 17:00 ` Andrew Jones 2024-04-23 17:00 ` Andrew Jones
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