From: Tomasz Jeznach <tjeznach@rivosinc.com> To: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, Paul Walmsley <paul.walmsley@sifive.com> Cc: Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <apatel@ventanamicro.com>, Sunil V L <sunilvl@ventanamicro.com>, Nick Kossifidis <mick@ics.forth.gr>, Sebastien Boeuf <seb@rivosinc.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, devicetree@vger.kernel.org, iommu@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux@rivosinc.com, Tomasz Jeznach <tjeznach@rivosinc.com> Subject: [PATCH v2 4/7] iommu/riscv: Enable IOMMU registration and device probe. Date: Thu, 18 Apr 2024 09:32:22 -0700 [thread overview] Message-ID: <c681ad581ddf644a288cac44ed4f7fdfd1acae0a.1713456598.git.tjeznach@rivosinc.com> (raw) In-Reply-To: <cover.1713456597.git.tjeznach@rivosinc.com> Advertise IOMMU device and its core API. Only minimal implementation for single identity domain type, without per-group domain protection. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> --- drivers/iommu/riscv/iommu.c | 69 +++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index af68c89200a9..d38317cb2493 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -18,6 +18,7 @@ #include <linux/iommu.h> #include <linux/kernel.h> #include <linux/module.h> +#include <linux/pci.h> #include "iommu-bits.h" #include "iommu.h" @@ -30,6 +31,67 @@ MODULE_LICENSE("GPL"); /* Timeouts in [us] */ #define RISCV_IOMMU_DDTP_TIMEOUT 50000 +static int riscv_iommu_attach_identity_domain(struct iommu_domain *domain, + struct device *dev) +{ + /* Global pass-through already enabled, do nothing for now. */ + return 0; +} + +static struct iommu_domain riscv_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &(const struct iommu_domain_ops) { + .attach_dev = riscv_iommu_attach_identity_domain, + } +}; + +static int riscv_iommu_device_domain_type(struct device *dev) +{ + return IOMMU_DOMAIN_IDENTITY; +} + +static struct iommu_group *riscv_iommu_device_group(struct device *dev) +{ + if (dev_is_pci(dev)) + return pci_device_group(dev); + return generic_device_group(dev); +} + +static int riscv_iommu_of_xlate(struct device *dev, const struct of_phandle_args *args) +{ + return iommu_fwspec_add_ids(dev, args->args, 1); +} + +static struct iommu_device *riscv_iommu_probe_device(struct device *dev) +{ + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct riscv_iommu_device *iommu; + + if (!fwspec->iommu_fwnode->dev || !fwspec->num_ids) + return ERR_PTR(-ENODEV); + + iommu = dev_get_drvdata(fwspec->iommu_fwnode->dev); + if (!iommu) + return ERR_PTR(-ENODEV); + + return &iommu->iommu; +} + +static void riscv_iommu_probe_finalize(struct device *dev) +{ + iommu_setup_dma_ops(dev, 0, U64_MAX); +} + +static const struct iommu_ops riscv_iommu_ops = { + .owner = THIS_MODULE, + .of_xlate = riscv_iommu_of_xlate, + .identity_domain = &riscv_iommu_identity_domain, + .def_domain_type = riscv_iommu_device_domain_type, + .device_group = riscv_iommu_device_group, + .probe_device = riscv_iommu_probe_device, + .probe_finalize = riscv_iommu_probe_finalize, +}; + static int riscv_iommu_init_check(struct riscv_iommu_device *iommu) { u64 ddtp; @@ -60,6 +122,7 @@ static int riscv_iommu_init_check(struct riscv_iommu_device *iommu) void riscv_iommu_remove(struct riscv_iommu_device *iommu) { + iommu_device_unregister(&iommu->iommu); iommu_device_sysfs_remove(&iommu->iommu); } @@ -82,8 +145,14 @@ int riscv_iommu_init(struct riscv_iommu_device *iommu) if (WARN(rc, "cannot register sysfs interface\n")) goto err_sysfs; + rc = iommu_device_register(&iommu->iommu, &riscv_iommu_ops, iommu->dev); + if (WARN(rc, "cannot register iommu interface\n")) + goto err_iommu; + return 0; +err_iommu: + iommu_device_sysfs_remove(&iommu->iommu); err_sysfs: return rc; } -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Tomasz Jeznach <tjeznach@rivosinc.com> To: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, Paul Walmsley <paul.walmsley@sifive.com> Cc: Anup Patel <apatel@ventanamicro.com>, devicetree@vger.kernel.org, Conor Dooley <conor+dt@kernel.org>, Albert Ou <aou@eecs.berkeley.edu>, Tomasz Jeznach <tjeznach@rivosinc.com>, linux@rivosinc.com, linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>, Sebastien Boeuf <seb@rivosinc.com>, iommu@lists.linux.dev, Palmer Dabbelt <palmer@dabbelt.com>, Nick Kossifidis <mick@ics.forth.gr>, Krzysztof Kozlowski <krzk+dt@kernel.org>, linux-riscv@lists.infradead.org Subject: [PATCH v2 4/7] iommu/riscv: Enable IOMMU registration and device probe. Date: Thu, 18 Apr 2024 09:32:22 -0700 [thread overview] Message-ID: <c681ad581ddf644a288cac44ed4f7fdfd1acae0a.1713456598.git.tjeznach@rivosinc.com> (raw) In-Reply-To: <cover.1713456597.git.tjeznach@rivosinc.com> Advertise IOMMU device and its core API. Only minimal implementation for single identity domain type, without per-group domain protection. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> --- drivers/iommu/riscv/iommu.c | 69 +++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index af68c89200a9..d38317cb2493 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -18,6 +18,7 @@ #include <linux/iommu.h> #include <linux/kernel.h> #include <linux/module.h> +#include <linux/pci.h> #include "iommu-bits.h" #include "iommu.h" @@ -30,6 +31,67 @@ MODULE_LICENSE("GPL"); /* Timeouts in [us] */ #define RISCV_IOMMU_DDTP_TIMEOUT 50000 +static int riscv_iommu_attach_identity_domain(struct iommu_domain *domain, + struct device *dev) +{ + /* Global pass-through already enabled, do nothing for now. */ + return 0; +} + +static struct iommu_domain riscv_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &(const struct iommu_domain_ops) { + .attach_dev = riscv_iommu_attach_identity_domain, + } +}; + +static int riscv_iommu_device_domain_type(struct device *dev) +{ + return IOMMU_DOMAIN_IDENTITY; +} + +static struct iommu_group *riscv_iommu_device_group(struct device *dev) +{ + if (dev_is_pci(dev)) + return pci_device_group(dev); + return generic_device_group(dev); +} + +static int riscv_iommu_of_xlate(struct device *dev, const struct of_phandle_args *args) +{ + return iommu_fwspec_add_ids(dev, args->args, 1); +} + +static struct iommu_device *riscv_iommu_probe_device(struct device *dev) +{ + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct riscv_iommu_device *iommu; + + if (!fwspec->iommu_fwnode->dev || !fwspec->num_ids) + return ERR_PTR(-ENODEV); + + iommu = dev_get_drvdata(fwspec->iommu_fwnode->dev); + if (!iommu) + return ERR_PTR(-ENODEV); + + return &iommu->iommu; +} + +static void riscv_iommu_probe_finalize(struct device *dev) +{ + iommu_setup_dma_ops(dev, 0, U64_MAX); +} + +static const struct iommu_ops riscv_iommu_ops = { + .owner = THIS_MODULE, + .of_xlate = riscv_iommu_of_xlate, + .identity_domain = &riscv_iommu_identity_domain, + .def_domain_type = riscv_iommu_device_domain_type, + .device_group = riscv_iommu_device_group, + .probe_device = riscv_iommu_probe_device, + .probe_finalize = riscv_iommu_probe_finalize, +}; + static int riscv_iommu_init_check(struct riscv_iommu_device *iommu) { u64 ddtp; @@ -60,6 +122,7 @@ static int riscv_iommu_init_check(struct riscv_iommu_device *iommu) void riscv_iommu_remove(struct riscv_iommu_device *iommu) { + iommu_device_unregister(&iommu->iommu); iommu_device_sysfs_remove(&iommu->iommu); } @@ -82,8 +145,14 @@ int riscv_iommu_init(struct riscv_iommu_device *iommu) if (WARN(rc, "cannot register sysfs interface\n")) goto err_sysfs; + rc = iommu_device_register(&iommu->iommu, &riscv_iommu_ops, iommu->dev); + if (WARN(rc, "cannot register iommu interface\n")) + goto err_iommu; + return 0; +err_iommu: + iommu_device_sysfs_remove(&iommu->iommu); err_sysfs: return rc; } -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-04-18 16:32 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-18 16:32 [PATCH v2 0/7] Linux RISC-V IOMMU Support Tomasz Jeznach 2024-04-18 16:32 ` Tomasz Jeznach 2024-04-18 16:32 ` [PATCH v2 1/7] dt-bindings: iommu: riscv: Add bindings for RISC-V IOMMU Tomasz Jeznach 2024-04-18 16:32 ` Tomasz Jeznach 2024-04-18 17:04 ` Conor Dooley 2024-04-18 17:04 ` Conor Dooley 2024-04-24 22:37 ` Tomasz Jeznach 2024-04-24 22:37 ` Tomasz Jeznach 2024-04-25 17:11 ` Conor Dooley 2024-04-25 17:11 ` Conor Dooley 2024-04-22 14:04 ` Rob Herring 2024-04-22 14:04 ` Rob Herring 2024-04-18 16:32 ` [PATCH v2 2/7] iommu/riscv: Add RISC-V IOMMU platform device driver Tomasz Jeznach 2024-04-18 16:32 ` Tomasz Jeznach 2024-04-18 21:22 ` Robin Murphy 2024-04-18 21:22 ` Robin Murphy 2024-04-24 21:59 ` Tomasz Jeznach 2024-04-24 21:59 ` Tomasz Jeznach 2024-04-25 11:23 ` Robin Murphy 2024-04-25 11:23 ` Robin Murphy 2024-04-18 16:32 ` [PATCH v2 3/7] iommu/riscv: Add RISC-V IOMMU PCIe " Tomasz Jeznach 2024-04-18 16:32 ` Tomasz Jeznach 2024-04-18 22:07 ` Robin Murphy 2024-04-18 22:07 ` Robin Murphy 2024-04-18 16:32 ` Tomasz Jeznach [this message] 2024-04-18 16:32 ` [PATCH v2 4/7] iommu/riscv: Enable IOMMU registration and device probe Tomasz Jeznach 2024-04-18 16:32 ` [PATCH v2 5/7] iommu/riscv: Device directory management Tomasz Jeznach 2024-04-18 16:32 ` Tomasz Jeznach 2024-04-19 12:40 ` Jason Gunthorpe 2024-04-19 12:40 ` Jason Gunthorpe 2024-04-24 23:01 ` Tomasz Jeznach 2024-04-24 23:01 ` Tomasz Jeznach 2024-04-24 23:07 ` Jason Gunthorpe 2024-04-24 23:07 ` Jason Gunthorpe 2024-04-22 5:11 ` Baolu Lu 2024-04-22 5:11 ` Baolu Lu 2024-04-24 23:07 ` Tomasz Jeznach 2024-04-24 23:07 ` Tomasz Jeznach 2024-04-18 16:32 ` [PATCH v2 6/7] iommu/riscv: Command and fault queue support Tomasz Jeznach 2024-04-18 16:32 ` Tomasz Jeznach 2024-04-18 16:32 ` [PATCH v2 7/7] iommu/riscv: Paging domain support Tomasz Jeznach 2024-04-18 16:32 ` Tomasz Jeznach 2024-04-19 12:56 ` Jason Gunthorpe 2024-04-19 12:56 ` Jason Gunthorpe 2024-04-22 7:40 ` Baolu Lu 2024-04-22 7:40 ` Baolu Lu 2024-04-24 23:30 ` Tomasz Jeznach 2024-04-24 23:30 ` Tomasz Jeznach 2024-04-24 23:39 ` Jason Gunthorpe 2024-04-24 23:39 ` Jason Gunthorpe 2024-04-24 23:54 ` Tomasz Jeznach 2024-04-24 23:54 ` Tomasz Jeznach 2024-04-25 0:48 ` Jason Gunthorpe 2024-04-25 0:48 ` Jason Gunthorpe 2024-04-22 5:21 ` Baolu Lu 2024-04-22 5:21 ` Baolu Lu 2024-04-22 19:30 ` Jason Gunthorpe 2024-04-22 19:30 ` Jason Gunthorpe 2024-04-23 17:00 ` Andrew Jones 2024-04-23 17:00 ` Andrew Jones
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