From: Roger Quadros <rogerq@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>, <tony@atomide.com>
Cc: <nm@ti.com>, <nsekhar@ti.com>, <balbi@ti.com>,
<grygorii.strashko@ti.com>, <linux-kernel@vger.kernel.org>,
<linux-omap@vger.kernel.org>
Subject: Re: [PATCH 2/3] phy: ti-pipe3: i783 workaround for SATA lockup after dpll unlock/relock
Date: Tue, 2 Jun 2015 11:17:06 +0300 [thread overview]
Message-ID: <556D6682.1030609@ti.com> (raw)
In-Reply-To: <555C89D2.5070301@ti.com>
Kishon,
On 20/05/15 16:19, Kishon Vijay Abraham I wrote:
> Hi Roger,
>
> On Tuesday 12 May 2015 09:37 PM, Roger Quadros wrote:
>> SATA_PLL_SOFT_RESET bit of CTRL_CORE_SMA_SW_0 must be toggled
>> between a SATA DPLL unlock and re-lock to prevent SATA lockup.
>>
>> Introduce a new DT parameter 'syscon-pllreset' to provide the syscon
>> regmap access to this register which sits in the control module.
>>
>> If the register is not provided we fallback to the old behaviour
>> i.e. SATA DPLL refclk will not be disabled and we prevent SoC low
>> power states.
>>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> ---
>> Documentation/devicetree/bindings/phy/ti-phy.txt | 16 ++++++
>> drivers/phy/phy-ti-pipe3.c | 67 ++++++++++++++++++++----
>> 2 files changed, 74 insertions(+), 9 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt
>> index 305e3df..f0f5537 100644
>> --- a/Documentation/devicetree/bindings/phy/ti-phy.txt
>> +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
>> @@ -82,6 +82,9 @@ Optional properties:
>> - id: If there are multiple instance of the same type, in order to
>> differentiate between each instance "id" can be used (e.g., multi-lane PCIe
>> PHY). If "id" is not provided, it is set to default value of '1'.
>> + - syscon-pllreset: Handle to system control region that contains the
>> + CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
>> + register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
>>
>> This is usually a subnode of ocp2scp to which it is connected.
>>
>> @@ -100,3 +103,16 @@ usb3phy@4a084400 {
>> "sysclk",
>> "refclk";
>> };
>> +
>> +sata_phy: phy@4A096000 {
>> + compatible = "ti,phy-pipe3-sata";
>> + reg = <0x4A096000 0x80>, /* phy_rx */
>> + <0x4A096400 0x64>, /* phy_tx */
>> + <0x4A096800 0x40>; /* pll_ctrl */
>> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
>> + ctrl-module = <&omap_control_sata>;
>> + clocks = <&sys_clkin1>, <&sata_ref_clk>;
>> + clock-names = "sysclk", "refclk";
>> + syscon-pllreset = <&dra7_ctrl_core 0x3fc>;
>> + #phy-cells = <0>;
>> +};
>> diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
>> index e13a306..d730142 100644
>> --- a/drivers/phy/phy-ti-pipe3.c
>> +++ b/drivers/phy/phy-ti-pipe3.c
>> @@ -28,6 +28,8 @@
>> #include <linux/delay.h>
>> #include <linux/phy/omap_control_phy.h>
>> #include <linux/of_platform.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/regmap.h>
>>
>> #define PLL_STATUS 0x00000004
>> #define PLL_GO 0x00000008
>> @@ -52,6 +54,8 @@
>> #define PLL_LOCK 0x2
>> #define PLL_IDLE 0x1
>>
>> +#define SATA_PLL_SOFT_RESET BIT(18)
>> +
>> /*
>> * This is an Empirical value that works, need to confirm the actual
>> * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
>> @@ -82,6 +86,9 @@ struct ti_pipe3 {
>> struct clk *refclk;
>> struct clk *div_clk;
>> struct pipe3_dpll_map *dpll_map;
>> + struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
>> + unsigned int dpll_reset_reg; /* reg. index within syscon */
>> + bool sata_refclk_enabled;
>> };
>>
>> static struct pipe3_dpll_map dpll_map_usb[] = {
>> @@ -249,11 +256,15 @@ static int ti_pipe3_exit(struct phy *x)
>> u32 val;
>> unsigned long timeout;
>>
>> - /* SATA DPLL can't be powered down due to Errata i783 and PCIe
>> - * does not have internal DPLL
>> + /* If dpll_reset_syscon is not present we wont power down SATA DPLL
>> + * due to Errata i783
>> */
>> - if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") ||
>> - of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
>> + if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") &&
>> + !phy->dpll_reset_syscon)
>> + return 0;
>> +
>> + /* PCIe doesn't have DPLL. FIXME: need to disable clocks though */
>
> I think it's better to fix it in this patch itself.. to disable clocks for PCIe.
I was not sure if it will break PCIe in any way. moreover it is not part of the patch subject.
do you still want me to fix it in this patch?
cheers,
-roger
WARNING: multiple messages have this Message-ID (diff)
From: Roger Quadros <rogerq@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>, tony@atomide.com
Cc: nm@ti.com, nsekhar@ti.com, balbi@ti.com,
grygorii.strashko@ti.com, linux-kernel@vger.kernel.org,
linux-omap@vger.kernel.org
Subject: Re: [PATCH 2/3] phy: ti-pipe3: i783 workaround for SATA lockup after dpll unlock/relock
Date: Tue, 2 Jun 2015 11:17:06 +0300 [thread overview]
Message-ID: <556D6682.1030609@ti.com> (raw)
In-Reply-To: <555C89D2.5070301@ti.com>
Kishon,
On 20/05/15 16:19, Kishon Vijay Abraham I wrote:
> Hi Roger,
>
> On Tuesday 12 May 2015 09:37 PM, Roger Quadros wrote:
>> SATA_PLL_SOFT_RESET bit of CTRL_CORE_SMA_SW_0 must be toggled
>> between a SATA DPLL unlock and re-lock to prevent SATA lockup.
>>
>> Introduce a new DT parameter 'syscon-pllreset' to provide the syscon
>> regmap access to this register which sits in the control module.
>>
>> If the register is not provided we fallback to the old behaviour
>> i.e. SATA DPLL refclk will not be disabled and we prevent SoC low
>> power states.
>>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> ---
>> Documentation/devicetree/bindings/phy/ti-phy.txt | 16 ++++++
>> drivers/phy/phy-ti-pipe3.c | 67 ++++++++++++++++++++----
>> 2 files changed, 74 insertions(+), 9 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt
>> index 305e3df..f0f5537 100644
>> --- a/Documentation/devicetree/bindings/phy/ti-phy.txt
>> +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
>> @@ -82,6 +82,9 @@ Optional properties:
>> - id: If there are multiple instance of the same type, in order to
>> differentiate between each instance "id" can be used (e.g., multi-lane PCIe
>> PHY). If "id" is not provided, it is set to default value of '1'.
>> + - syscon-pllreset: Handle to system control region that contains the
>> + CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
>> + register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
>>
>> This is usually a subnode of ocp2scp to which it is connected.
>>
>> @@ -100,3 +103,16 @@ usb3phy@4a084400 {
>> "sysclk",
>> "refclk";
>> };
>> +
>> +sata_phy: phy@4A096000 {
>> + compatible = "ti,phy-pipe3-sata";
>> + reg = <0x4A096000 0x80>, /* phy_rx */
>> + <0x4A096400 0x64>, /* phy_tx */
>> + <0x4A096800 0x40>; /* pll_ctrl */
>> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
>> + ctrl-module = <&omap_control_sata>;
>> + clocks = <&sys_clkin1>, <&sata_ref_clk>;
>> + clock-names = "sysclk", "refclk";
>> + syscon-pllreset = <&dra7_ctrl_core 0x3fc>;
>> + #phy-cells = <0>;
>> +};
>> diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
>> index e13a306..d730142 100644
>> --- a/drivers/phy/phy-ti-pipe3.c
>> +++ b/drivers/phy/phy-ti-pipe3.c
>> @@ -28,6 +28,8 @@
>> #include <linux/delay.h>
>> #include <linux/phy/omap_control_phy.h>
>> #include <linux/of_platform.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/regmap.h>
>>
>> #define PLL_STATUS 0x00000004
>> #define PLL_GO 0x00000008
>> @@ -52,6 +54,8 @@
>> #define PLL_LOCK 0x2
>> #define PLL_IDLE 0x1
>>
>> +#define SATA_PLL_SOFT_RESET BIT(18)
>> +
>> /*
>> * This is an Empirical value that works, need to confirm the actual
>> * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
>> @@ -82,6 +86,9 @@ struct ti_pipe3 {
>> struct clk *refclk;
>> struct clk *div_clk;
>> struct pipe3_dpll_map *dpll_map;
>> + struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
>> + unsigned int dpll_reset_reg; /* reg. index within syscon */
>> + bool sata_refclk_enabled;
>> };
>>
>> static struct pipe3_dpll_map dpll_map_usb[] = {
>> @@ -249,11 +256,15 @@ static int ti_pipe3_exit(struct phy *x)
>> u32 val;
>> unsigned long timeout;
>>
>> - /* SATA DPLL can't be powered down due to Errata i783 and PCIe
>> - * does not have internal DPLL
>> + /* If dpll_reset_syscon is not present we wont power down SATA DPLL
>> + * due to Errata i783
>> */
>> - if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") ||
>> - of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
>> + if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") &&
>> + !phy->dpll_reset_syscon)
>> + return 0;
>> +
>> + /* PCIe doesn't have DPLL. FIXME: need to disable clocks though */
>
> I think it's better to fix it in this patch itself.. to disable clocks for PCIe.
I was not sure if it will break PCIe in any way. moreover it is not part of the patch subject.
do you still want me to fix it in this patch?
cheers,
-roger
next prev parent reply other threads:[~2015-06-02 8:17 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-12 16:07 [PATCH 0/3] phy: ti-pipe3: dra7: sata: allow suspend to RAM Roger Quadros
2015-05-12 16:07 ` Roger Quadros
2015-05-12 16:07 ` [PATCH 1/3] phy: ti-pipe3: fix suspend Roger Quadros
2015-05-12 16:07 ` Roger Quadros
2015-05-20 13:04 ` Kishon Vijay Abraham I
2015-05-20 13:04 ` Kishon Vijay Abraham I
2015-05-20 13:48 ` Roger Quadros
2015-05-20 13:48 ` Roger Quadros
2015-05-12 16:07 ` [PATCH 2/3] phy: ti-pipe3: i783 workaround for SATA lockup after dpll unlock/relock Roger Quadros
2015-05-12 16:07 ` Roger Quadros
2015-05-20 13:19 ` Kishon Vijay Abraham I
2015-05-20 13:19 ` Kishon Vijay Abraham I
2015-05-20 13:47 ` Roger Quadros
2015-05-20 13:47 ` Roger Quadros
2015-05-22 11:34 ` Kishon Vijay Abraham I
2015-05-22 11:34 ` Kishon Vijay Abraham I
2015-05-22 13:58 ` Roger Quadros
2015-05-22 13:58 ` Roger Quadros
2015-05-23 7:22 ` Kishon Vijay Abraham I
2015-05-23 7:22 ` Kishon Vijay Abraham I
2015-05-26 14:20 ` Roger Quadros
2015-05-26 14:20 ` Roger Quadros
2015-06-02 8:17 ` Roger Quadros [this message]
2015-06-02 8:17 ` Roger Quadros
2015-05-12 16:07 ` [PATCH 3/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY Roger Quadros
2015-05-12 16:07 ` Roger Quadros
2015-07-14 10:34 ` Tony Lindgren
2015-07-14 10:39 ` Roger Quadros
2015-07-14 10:39 ` Roger Quadros
-- strict thread matches above, loose matches on Subject: below --
2015-08-04 16:47 [GIT PULL 0/3] phy: for 4.2 -rc Kishon Vijay Abraham I
2015-08-04 16:47 ` [PATCH 2/3] phy: ti-pipe3: i783 workaround for SATA lockup after dpll unlock/relock Kishon Vijay Abraham I
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