From: BALATON Zoltan <balaton@eik.bme.hu>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org,
Daniel Henrique Barboza <danielhb413@gmail.com>,
qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [PATCH v4 18/24] ppc/ppc405: QOM'ify MAL
Date: Wed, 10 Aug 2022 23:35:46 +0200 (CEST) [thread overview]
Message-ID: <60aac5fd-a7ed-9c44-21b7-c563c3438ebb@eik.bme.hu> (raw)
In-Reply-To: <20220809153904.485018-19-clg@kaod.org>
[-- Attachment #1: Type: text/plain, Size: 12758 bytes --]
On Tue, 9 Aug 2022, Cédric Le Goater wrote:
> The Memory Access Layer (MAL) controller is currently modeled as a DCR
> device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt
> the sam460ex machine.
>
> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405.h | 1 +
> include/hw/ppc/ppc4xx.h | 32 +++++++++-
> hw/ppc/ppc405_uc.c | 18 ++++--
> hw/ppc/ppc4xx_devs.c | 135 ++++++++++++++++++----------------------
> hw/ppc/sam460ex.c | 16 +++--
> 5 files changed, 116 insertions(+), 86 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index cb34792daf6b..31c94e474209 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -244,6 +244,7 @@ struct Ppc405SoCState {
> Ppc405OpbaState opba;
> Ppc405PobState pob;
> Ppc405PlbState plb;
> + Ppc4xxMalState mal;
> };
>
> /* PowerPC 405 core */
> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
> index 82e60b0e0742..acd096cb2394 100644
> --- a/include/hw/ppc/ppc4xx.h
> +++ b/include/hw/ppc/ppc4xx.h
> @@ -26,6 +26,7 @@
> #define PPC4XX_H
>
> #include "hw/ppc/ppc.h"
> +#include "hw/sysbus.h"
Is this needed?
> #include "exec/memory.h"
> #include "hw/sysbus.h"
>
> @@ -40,9 +41,6 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
> hwaddr *ram_sizes,
> int do_init);
>
> -void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
> - qemu_irq irqs[4]);
> -
> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>
> /*
> @@ -61,4 +59,32 @@ void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn,
> bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
> Error **errp);
>
> +/* Memory Access Layer (MAL) */
> +#define TYPE_PPC4xx_MAL "ppc4xx-mal"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL);
> +struct Ppc4xxMalState {
> + Ppc4xxDcrDeviceState parent_obj;
> +
> + qemu_irq irqs[4];
> + uint32_t cfg;
> + uint32_t esr;
> + uint32_t ier;
> + uint32_t txcasr;
> + uint32_t txcarr;
> + uint32_t txeobisr;
> + uint32_t txdeir;
> + uint32_t rxcasr;
> + uint32_t rxcarr;
> + uint32_t rxeobisr;
> + uint32_t rxdeir;
> + uint32_t *txctpr;
> + uint32_t *rxctpr;
> + uint32_t *rcbs;
> + uint8_t txcnum;
> + uint8_t rxcnum;
> +};
> +
> +void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
> + qemu_irq irqs[4]);
The ppc4xx_mal_init func is gone so this declaration should also be
dropped.
Regards,
BALATON Zoltan
> +
> #endif /* PPC4XX_H */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 7f4c616da67c..290cfa352bed 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1368,6 +1368,8 @@ static void ppc405_soc_instance_init(Object *obj)
> object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
>
> object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB);
> +
> + object_initialize_child(obj, "mal", &s->mal, TYPE_PPC4xx_MAL);
> }
>
> static void ppc405_reset(void *opaque)
> @@ -1378,7 +1380,6 @@ static void ppc405_reset(void *opaque)
> static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> {
> Ppc405SoCState *s = PPC405_SOC(dev);
> - qemu_irq mal_irqs[4];
> CPUPPCState *env;
> int i;
>
> @@ -1495,11 +1496,16 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> }
>
> /* MAL */
> - mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
> - mal_irqs[1] = qdev_get_gpio_in(s->uic, 12);
> - mal_irqs[2] = qdev_get_gpio_in(s->uic, 13);
> - mal_irqs[3] = qdev_get_gpio_in(s->uic, 14);
> - ppc4xx_mal_init(env, 4, 2, mal_irqs);
> + object_property_set_int(OBJECT(&s->mal), "txc-num", 4, &error_abort);
> + object_property_set_int(OBJECT(&s->mal), "rxc-num", 2, &error_abort);
> + if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->mal), &s->cpu, errp)) {
> + return;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->mal), i,
> + qdev_get_gpio_in(s->uic, 11 + i));
> + }
>
> /* Ethernet */
> /* Uses UIC IRQs 9, 15, 17 */
> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
> index bce7ef461346..8a8a87b03b28 100644
> --- a/hw/ppc/ppc4xx_devs.c
> +++ b/hw/ppc/ppc4xx_devs.c
> @@ -459,32 +459,10 @@ enum {
> MAL0_RCBS1 = 0x1E1,
> };
>
> -typedef struct ppc4xx_mal_t ppc4xx_mal_t;
> -struct ppc4xx_mal_t {
> - qemu_irq irqs[4];
> - uint32_t cfg;
> - uint32_t esr;
> - uint32_t ier;
> - uint32_t txcasr;
> - uint32_t txcarr;
> - uint32_t txeobisr;
> - uint32_t txdeir;
> - uint32_t rxcasr;
> - uint32_t rxcarr;
> - uint32_t rxeobisr;
> - uint32_t rxdeir;
> - uint32_t *txctpr;
> - uint32_t *rxctpr;
> - uint32_t *rcbs;
> - uint8_t txcnum;
> - uint8_t rxcnum;
> -};
> -
> -static void ppc4xx_mal_reset(void *opaque)
> +static void ppc4xx_mal_reset(DeviceState *dev)
> {
> - ppc4xx_mal_t *mal;
> + Ppc4xxMalState *mal = PPC4xx_MAL(dev);
>
> - mal = opaque;
> mal->cfg = 0x0007C000;
> mal->esr = 0x00000000;
> mal->ier = 0x00000000;
> @@ -498,10 +476,9 @@ static void ppc4xx_mal_reset(void *opaque)
>
> static uint32_t dcr_read_mal(void *opaque, int dcrn)
> {
> - ppc4xx_mal_t *mal;
> + Ppc4xxMalState *mal = PPC4xx_MAL(opaque);
> uint32_t ret;
>
> - mal = opaque;
> switch (dcrn) {
> case MAL0_CFG:
> ret = mal->cfg;
> @@ -555,13 +532,12 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn)
>
> static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
> {
> - ppc4xx_mal_t *mal;
> + Ppc4xxMalState *mal = PPC4xx_MAL(opaque);
>
> - mal = opaque;
> switch (dcrn) {
> case MAL0_CFG:
> if (val & 0x80000000) {
> - ppc4xx_mal_reset(mal);
> + ppc4xx_mal_reset(DEVICE(mal));
> }
> mal->cfg = val & 0x00FFC087;
> break;
> @@ -612,59 +588,67 @@ static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
> }
> }
>
> -void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
> - qemu_irq irqs[4])
> +static void ppc4xx_mal_realize(DeviceState *dev, Error **errp)
> {
> - ppc4xx_mal_t *mal;
> + Ppc4xxMalState *mal = PPC4xx_MAL(dev);
> + Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
> int i;
>
> - assert(txcnum <= 32 && rxcnum <= 32);
> - mal = g_malloc0(sizeof(*mal));
> - mal->txcnum = txcnum;
> - mal->rxcnum = rxcnum;
> - mal->txctpr = g_new0(uint32_t, txcnum);
> - mal->rxctpr = g_new0(uint32_t, rxcnum);
> - mal->rcbs = g_new0(uint32_t, rxcnum);
> - for (i = 0; i < 4; i++) {
> - mal->irqs[i] = irqs[i];
> + if (mal->txcnum > 32 || mal->rxcnum > 32) {
> + error_setg(errp, "invalid TXC/RXC number");
> + return;
> + }
> +
> + mal->txctpr = g_new0(uint32_t, mal->txcnum);
> + mal->rxctpr = g_new0(uint32_t, mal->rxcnum);
> + mal->rcbs = g_new0(uint32_t, mal->rxcnum);
> +
> + for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) {
> + sysbus_init_irq(SYS_BUS_DEVICE(dev), &mal->irqs[i]);
> }
> - qemu_register_reset(&ppc4xx_mal_reset, mal);
> - ppc_dcr_register(env, MAL0_CFG,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_ESR,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_IER,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_TXCASR,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_TXCARR,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_TXEOBISR,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_TXDEIR,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_RXCASR,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_RXCARR,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_RXEOBISR,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_RXDEIR,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - for (i = 0; i < txcnum; i++) {
> - ppc_dcr_register(env, MAL0_TXCTP0R + i,
> - mal, &dcr_read_mal, &dcr_write_mal);
> +
> + ppc4xx_dcr_register(dcr, MAL0_CFG, &dcr_read_mal, &dcr_write_mal);
> + ppc4xx_dcr_register(dcr, MAL0_ESR, &dcr_read_mal, &dcr_write_mal);
> + ppc4xx_dcr_register(dcr, MAL0_IER, &dcr_read_mal, &dcr_write_mal);
> + ppc4xx_dcr_register(dcr, MAL0_TXCASR, &dcr_read_mal, &dcr_write_mal);
> + ppc4xx_dcr_register(dcr, MAL0_TXCARR, &dcr_read_mal, &dcr_write_mal);
> + ppc4xx_dcr_register(dcr, MAL0_TXEOBISR, &dcr_read_mal, &dcr_write_mal);
> + ppc4xx_dcr_register(dcr, MAL0_TXDEIR, &dcr_read_mal, &dcr_write_mal);
> + ppc4xx_dcr_register(dcr, MAL0_RXCASR, &dcr_read_mal, &dcr_write_mal);
> + ppc4xx_dcr_register(dcr, MAL0_RXCARR, &dcr_read_mal, &dcr_write_mal);
> + ppc4xx_dcr_register(dcr, MAL0_RXEOBISR, &dcr_read_mal, &dcr_write_mal);
> + ppc4xx_dcr_register(dcr, MAL0_RXDEIR, &dcr_read_mal, &dcr_write_mal);
> + for (i = 0; i < mal->txcnum; i++) {
> + ppc4xx_dcr_register(dcr, MAL0_TXCTP0R + i,
> + &dcr_read_mal, &dcr_write_mal);
> }
> - for (i = 0; i < rxcnum; i++) {
> - ppc_dcr_register(env, MAL0_RXCTP0R + i,
> - mal, &dcr_read_mal, &dcr_write_mal);
> + for (i = 0; i < mal->rxcnum; i++) {
> + ppc4xx_dcr_register(dcr, MAL0_RXCTP0R + i,
> + &dcr_read_mal, &dcr_write_mal);
> }
> - for (i = 0; i < rxcnum; i++) {
> - ppc_dcr_register(env, MAL0_RCBS0 + i,
> - mal, &dcr_read_mal, &dcr_write_mal);
> + for (i = 0; i < mal->rxcnum; i++) {
> + ppc4xx_dcr_register(dcr, MAL0_RCBS0 + i,
> + &dcr_read_mal, &dcr_write_mal);
> }
> }
>
> +static Property ppc4xx_mal_properties[] = {
> + DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0),
> + DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void ppc4xx_mal_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc4xx_mal_realize;
> + dc->user_creatable = false;
> + /* Reason: only works as function of a ppc4xx SoC */
> + dc->reset = ppc4xx_mal_reset;
> + device_class_set_props(dc, ppc4xx_mal_properties);
> +}
> +
> void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn,
> dcr_read_cb dcr_read, dcr_write_cb dcr_write)
> {
> @@ -699,6 +683,11 @@ static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo ppc4xx_types[] = {
> {
> + .name = TYPE_PPC4xx_MAL,
> + .parent = TYPE_PPC4xx_DCR_DEVICE,
> + .instance_size = sizeof(Ppc4xxMalState),
> + .class_init = ppc4xx_mal_class_init,
> + }, {
> .name = TYPE_PPC4xx_DCR_DEVICE,
> .parent = TYPE_SYS_BUS_DEVICE,
> .instance_size = sizeof(Ppc4xxDcrDeviceState),
> diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
> index 31139c1554de..5f0e0ccaf485 100644
> --- a/hw/ppc/sam460ex.c
> +++ b/hw/ppc/sam460ex.c
> @@ -280,7 +280,7 @@ static void sam460ex_init(MachineState *machine)
> hwaddr ram_sizes[SDRAM_NR_BANKS] = {0};
> MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
> DeviceState *uic[4];
> - qemu_irq mal_irqs[4];
> + Ppc4xxMalState *mal;
> int i;
> PCIBus *pci_bus;
> PowerPCCPU *cpu;
> @@ -387,10 +387,18 @@ static void sam460ex_init(MachineState *machine)
> ppc4xx_sdr_init(env);
>
> /* MAL */
> - for (i = 0; i < ARRAY_SIZE(mal_irqs); i++) {
> - mal_irqs[i] = qdev_get_gpio_in(uic[2], 3 + i);
> + dev = qdev_new(TYPE_PPC4xx_MAL);
> + mal = PPC4xx_MAL(dev);
> +
> + qdev_prop_set_uint32(dev, "txc-num", 4);
> + qdev_prop_set_uint32(dev, "rxc-num", 16);
> + ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(mal), cpu, &error_fatal);
> + object_unref(OBJECT(mal));
> +
> + for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) {
> + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
> + qdev_get_gpio_in(uic[2], 3 + i));
> }
> - ppc4xx_mal_init(env, 4, 16, mal_irqs);
>
> /* DMA */
> ppc4xx_dma_init(env, 0x200);
>
next prev parent reply other threads:[~2022-08-10 21:37 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-09 15:38 [PATCH v4 00/24] ppc: QOM'ify 405 board Cédric Le Goater
2022-08-09 15:38 ` [PATCH v4 01/24] ppc/ppc405: Remove taihu machine Cédric Le Goater
2022-08-09 15:38 ` [PATCH v4 02/24] ppc/ppc405: Introduce a PPC405 generic machine Cédric Le Goater
2022-08-09 15:38 ` [PATCH v4 03/24] ppc/ppc405: Move devices under the ref405ep machine Cédric Le Goater
2022-08-09 15:38 ` [PATCH v4 04/24] ppc/ppc405: Move SRAM " Cédric Le Goater
2022-08-09 16:53 ` BALATON Zoltan
2022-08-09 17:42 ` Cédric Le Goater
2022-08-09 15:38 ` [PATCH v4 05/24] ppc/ppc405: Introduce a PPC405 SoC Cédric Le Goater
2022-08-09 16:59 ` BALATON Zoltan
2022-08-09 15:38 ` [PATCH v4 06/24] ppc/ppc405: Start QOMification of the SoC Cédric Le Goater
2022-08-09 17:12 ` BALATON Zoltan
2022-08-09 15:38 ` [PATCH v4 07/24] ppc/ppc405: QOM'ify CPU Cédric Le Goater
2022-08-09 17:15 ` BALATON Zoltan
2022-08-09 17:39 ` BALATON Zoltan
2022-08-09 15:38 ` [PATCH v4 08/24] ppc/ppc4xx: Introduce a DCR device model Cédric Le Goater
2022-08-09 17:21 ` BALATON Zoltan
2022-08-10 12:38 ` Cédric Le Goater
2022-08-10 13:28 ` BALATON Zoltan
2022-08-10 13:57 ` Cédric Le Goater
2022-08-10 14:48 ` BALATON Zoltan
2022-08-11 7:09 ` Cédric Le Goater
2022-08-11 11:39 ` BALATON Zoltan
2022-08-11 12:20 ` Cédric Le Goater
2022-08-11 21:55 ` BALATON Zoltan
2022-08-09 15:38 ` [PATCH v4 09/24] ppc/ppc405: QOM'ify CPC Cédric Le Goater
2022-08-09 15:38 ` [PATCH v4 10/24] ppc/ppc405: QOM'ify GPT Cédric Le Goater
2022-08-09 15:38 ` [PATCH v4 11/24] ppc/ppc405: QOM'ify OCM Cédric Le Goater
2022-08-09 15:38 ` [PATCH v4 12/24] ppc/ppc405: QOM'ify GPIO Cédric Le Goater
2022-08-09 15:38 ` [PATCH v4 13/24] ppc/ppc405: QOM'ify DMA Cédric Le Goater
2022-08-09 15:38 ` [PATCH v4 14/24] ppc/ppc405: QOM'ify EBC Cédric Le Goater
2022-08-09 15:38 ` [PATCH v4 15/24] ppc/ppc405: QOM'ify OPBA Cédric Le Goater
2022-08-09 15:38 ` [PATCH v4 16/24] ppc/ppc405: QOM'ify POB Cédric Le Goater
2022-08-09 15:38 ` [PATCH v4 17/24] ppc/ppc405: QOM'ify PLB Cédric Le Goater
2022-08-09 15:38 ` [PATCH v4 18/24] ppc/ppc405: QOM'ify MAL Cédric Le Goater
2022-08-09 17:34 ` BALATON Zoltan
2022-08-10 6:17 ` Cédric Le Goater
2022-08-10 21:35 ` BALATON Zoltan [this message]
2022-08-09 15:38 ` [PATCH v4 19/24] ppc/ppc405: QOM'ify FPGA Cédric Le Goater
2022-08-09 17:37 ` BALATON Zoltan
2022-08-10 6:22 ` Cédric Le Goater
2022-08-10 11:40 ` BALATON Zoltan
2022-08-10 17:22 ` Daniel Henrique Barboza
2022-08-10 17:32 ` BALATON Zoltan
2022-08-09 15:39 ` [PATCH v4 20/24] ppc/ppc405: Use an embedded PPCUIC model in SoC state Cédric Le Goater
2022-08-09 17:40 ` BALATON Zoltan
2022-08-09 15:39 ` [PATCH v4 21/24] ppc/ppc405: Use an explicit I2C object Cédric Le Goater
2022-08-09 17:45 ` BALATON Zoltan
2022-08-09 15:39 ` [PATCH v4 22/24] ppc/ppc4xx: Fix sdram trace events Cédric Le Goater
2022-08-09 17:47 ` BALATON Zoltan
2022-08-09 15:39 ` [PATCH v4 23/24] ppc/ppc405: QOM'ify SDRAM Cédric Le Goater
2022-08-09 17:53 ` BALATON Zoltan
2022-08-10 6:26 ` Cédric Le Goater
2022-08-10 11:39 ` BALATON Zoltan
2022-08-09 15:39 ` [PATCH v4 24/24] ppc/ppc405: Add check on minimum RAM size Cédric Le Goater
2022-08-09 17:55 ` BALATON Zoltan
2022-08-10 6:24 ` Cédric Le Goater
2022-08-11 8:24 ` [PATCH v4 00/24] ppc: QOM'ify 405 board Daniel Henrique Barboza
2022-08-11 8:33 ` Cédric Le Goater
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