* [PATCH 0/4 v4] PCI: Add Secondary Bus Reset (SBR) support for CXL
@ 2024-04-09 16:01 Dave Jiang
2024-04-09 16:01 ` [PATCH v4 1/4] PCI/cxl: Move PCI CXL vendor Id to a common location from CXL subsystem Dave Jiang
` (3 more replies)
0 siblings, 4 replies; 15+ messages in thread
From: Dave Jiang @ 2024-04-09 16:01 UTC (permalink / raw)
To: linux-cxl, linux-pci
Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield,
Jonathan.Cameron, dave, bhelgaas, lukas
Hi Bjorn,
Please consider this series for kernel 6.10. The series attempt to
add secondary bus reset (SBR) support to CXL. By default, SBR for CXL is
masked. Per CXL specification r3.1 8.1.5.2, the Port Control Extensions
register bit 0 (Unmask SBR) in the host bridge controls the masking of CXL SBR.
"When 0, SBR bit in Bridge Control register of this Port has no effect. When 1,
the Port shall generate hot reset when SBR in Bridge Control gets set to 1.
Default value of this bit is 0. When the Port is operating in PCIe mode or RCD
mode, this field has no effect on SBR functionality and Port shall follow PCIe
Base Specification."
v4:
- Return u16 for cxl_port_dvsec(). (Lukas)
- Use pci_dev_lock guard() on bridge. (Lukas)
- Clarify commit subject on 4/4. (Jonathan)
v3:
- Move PCI_DVSEC_VENDOR_ID_CXL to PCI_VENDOR_ID_CXL in pci_ids.h (Bjorn)
- Remove of CXL device checking. (Bjorn)
- Rename defines to PCI_DVSEC_CXL_PORT_*. (Bjorn)
- Fix SBR define in commit log. (Bjorn)
- Update comment on dvsec not found. (Dan)
- Check return of dvsec value read for error. (Dan)
- Move cxl_port_dvsec() to an earlier patch. (Dan)
- Add pci_cfg_access_lock() for bridge access. (Dan)
- Change cxl_bus_force method to cxl_bus. (Dan)
- Rename decoder_hw_mismatch() to __cxl_endpoint_decoder_reset_detected(). (Dan)
- Move CXL register access function to core/pci.c. (Dan)
- Add kernel taint to decoder reset warning. (Dan)
v2:
- Use pci_upstream_bridge() instead of dev->bus->self. (Lukas)
- Rename is_cxl_device() to pci_is_cxl(). (Lukas)
- Return -ENOTTY on error. (Lukas)
Patch 1:
Move PCI_DVSEC_VENDOR_ID_CXL to PCI_VENDOR_ID_CXL in pci_ids.h and adjust related
CXL bits.
Patch 2:
Add check to PCI bus_reset path for CXL device and return with error if "Unmask
SBR" bit is set to 0. This allows user to realize that SBR is masked for this
CXL device. However, if the user sets the "Unmask SBR" bit via a tool such as
setpci, then the bus_reset will proceed.
Patch3:
Add a new PCI reset method "cxl_bus" in order to allow the user an
intetional way to perform SBR. The code will set the "Unmask SBR" bit to
1 and proceed with bus_reset. The original value of the bit will be restored
after the reset operation.
Patch4:
CXL driver change that provides a ->reset_done() callback. It compares the
hardware decoder settings with the existing software configuration and emit
warning if they differ. The difference indicates that decoders were programmed
before the reset and are now cleared after reset. There may be onlined system
memory backed by CXL memory device that are now violently ripped away from
kernel mapping.
Patch series stemmed from this [1] patch. With comments [2] from Bjorn.
[1]: https://lore.kernel.org/linux-cxl/20240215232307.2793530-1-dave.jiang@intel.com/
[2]: https://lore.kernel.org/linux-cxl/20240220203956.GA1502351@bhelgaas/
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v4 1/4] PCI/cxl: Move PCI CXL vendor Id to a common location from CXL subsystem
2024-04-09 16:01 [PATCH 0/4 v4] PCI: Add Secondary Bus Reset (SBR) support for CXL Dave Jiang
@ 2024-04-09 16:01 ` Dave Jiang
2024-04-09 21:28 ` Kuppuswamy Sathyanarayanan
2024-04-09 22:51 ` Dan Williams
2024-04-09 16:01 ` [PATCH v4 2/4] PCI: Add check for CXL Secondary Bus Reset Dave Jiang
` (2 subsequent siblings)
3 siblings, 2 replies; 15+ messages in thread
From: Dave Jiang @ 2024-04-09 16:01 UTC (permalink / raw)
To: linux-cxl, linux-pci
Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield,
Jonathan.Cameron, dave, bhelgaas, lukas, Bjorn Helgaas
Move PCI_DVSEC_VENDOR_ID_CXL in CXL private code to PCI_VENDOR_ID_CXL in
pci_ids.h in order to be utilized in PCI subsystem.
The response Bjorn received from the PCI SIG was "1E98h is not a VID in our
system, but 1E98 has already been reserved by CXL." He suggested "we should
add '#define PCI_VENDOR_ID_CXL 0x1e98' so that if we ever *do* see such an
assignment, we'll be more likely to flag it as an issue.
Link: https://lore.kernel.org/linux-cxl/20240402172323.GA1818777@bhelgaas/
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/core/pci.c | 6 +++---
drivers/cxl/core/regs.c | 2 +-
drivers/cxl/cxlpci.h | 1 -
drivers/cxl/pci.c | 2 +-
drivers/perf/cxl_pmu.c | 2 +-
include/linux/pci_ids.h | 2 ++
6 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 0df09bd79408..c496a9710d62 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -525,7 +525,7 @@ static int cxl_cdat_get_length(struct device *dev,
__le32 response[2];
int rc;
- rc = pci_doe(doe_mb, PCI_DVSEC_VENDOR_ID_CXL,
+ rc = pci_doe(doe_mb, PCI_VENDOR_ID_CXL,
CXL_DOE_PROTOCOL_TABLE_ACCESS,
&request, sizeof(request),
&response, sizeof(response));
@@ -555,7 +555,7 @@ static int cxl_cdat_read_table(struct device *dev,
__le32 request = CDAT_DOE_REQ(entry_handle);
int rc;
- rc = pci_doe(doe_mb, PCI_DVSEC_VENDOR_ID_CXL,
+ rc = pci_doe(doe_mb, PCI_VENDOR_ID_CXL,
CXL_DOE_PROTOCOL_TABLE_ACCESS,
&request, sizeof(request),
rsp, sizeof(*rsp) + remaining);
@@ -640,7 +640,7 @@ void read_cdat_data(struct cxl_port *port)
if (!pdev)
return;
- doe_mb = pci_find_doe_mailbox(pdev, PCI_DVSEC_VENDOR_ID_CXL,
+ doe_mb = pci_find_doe_mailbox(pdev, PCI_VENDOR_ID_CXL,
CXL_DOE_PROTOCOL_TABLE_ACCESS);
if (!doe_mb) {
dev_dbg(dev, "No CDAT mailbox\n");
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 372786f80955..da52fc9e234b 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -313,7 +313,7 @@ int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type,
.resource = CXL_RESOURCE_NONE,
};
- regloc = pci_find_dvsec_capability(pdev, PCI_DVSEC_VENDOR_ID_CXL,
+ regloc = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
CXL_DVSEC_REG_LOCATOR);
if (!regloc)
return -ENXIO;
diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index 93992a1c8eec..4da07727ab9c 100644
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -13,7 +13,6 @@
* "DVSEC" redundancies removed. When obvious, abbreviations may be used.
*/
#define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20)
-#define PCI_DVSEC_VENDOR_ID_CXL 0x1E98
/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
#define CXL_DVSEC_PCIE_DEVICE 0
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 2ff361e756d6..110478573296 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -817,7 +817,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
cxlds->rcd = is_cxl_restricted(pdev);
cxlds->serial = pci_get_dsn(pdev);
cxlds->cxl_dvsec = pci_find_dvsec_capability(
- pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE);
+ pdev, PCI_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE);
if (!cxlds->cxl_dvsec)
dev_warn(&pdev->dev,
"Device DVSEC not present, skip CXL.mem init\n");
diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c
index 308c9969642e..a1b742b1a735 100644
--- a/drivers/perf/cxl_pmu.c
+++ b/drivers/perf/cxl_pmu.c
@@ -345,7 +345,7 @@ static ssize_t cxl_pmu_event_sysfs_show(struct device *dev,
/* For CXL spec defined events */
#define CXL_PMU_EVENT_CXL_ATTR(_name, _gid, _msk) \
- CXL_PMU_EVENT_ATTR(_name, PCI_DVSEC_VENDOR_ID_CXL, _gid, _msk)
+ CXL_PMU_EVENT_ATTR(_name, PCI_VENDOR_ID_CXL, _gid, _msk)
static struct attribute *cxl_pmu_event_attrs[] = {
CXL_PMU_EVENT_CXL_ATTR(clock_ticks, CXL_PMU_GID_CLOCK_TICKS, BIT(0)),
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index a0c75e467df3..7dfbf6d96b3d 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2607,6 +2607,8 @@
#define PCI_VENDOR_ID_ALIBABA 0x1ded
+#define PCI_VENDOR_ID_CXL 0x1e98
+
#define PCI_VENDOR_ID_TEHUTI 0x1fc9
#define PCI_DEVICE_ID_TEHUTI_3009 0x3009
#define PCI_DEVICE_ID_TEHUTI_3010 0x3010
--
2.44.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v4 2/4] PCI: Add check for CXL Secondary Bus Reset
2024-04-09 16:01 [PATCH 0/4 v4] PCI: Add Secondary Bus Reset (SBR) support for CXL Dave Jiang
2024-04-09 16:01 ` [PATCH v4 1/4] PCI/cxl: Move PCI CXL vendor Id to a common location from CXL subsystem Dave Jiang
@ 2024-04-09 16:01 ` Dave Jiang
2024-04-09 21:39 ` Kuppuswamy Sathyanarayanan
2024-04-09 22:56 ` Dan Williams
2024-04-09 16:01 ` [PATCH v4 3/4] PCI: Create new reset method to force SBR for CXL Dave Jiang
2024-04-09 16:01 ` [PATCH v4 4/4] cxl: Add post reset warning if reset results in loss of previously committed HDM decoders Dave Jiang
3 siblings, 2 replies; 15+ messages in thread
From: Dave Jiang @ 2024-04-09 16:01 UTC (permalink / raw)
To: linux-cxl, linux-pci
Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield,
Jonathan.Cameron, dave, bhelgaas, lukas
Per CXL spec r3.1 8.1.5.2, Secondary Bus Reset (SBR) is masked unless the
"Unmask SBR" bit is set. Add a check to the PCI secondary bus reset
path to fail the CXL SBR request if the "Unmask SBR" bit is clear in
the CXL Port Control Extensions register by returning -ENOTTY.
When the "Unmask SBR" bit is set to 0 (default), the bus_reset would
appear to have executed successfully. However the operation is actually
masked. The intention is to inform the user that SBR for the CXL device
is masked and will not go through.
If the "Unmask SBR" bit is set to 1, then the bus reset will execute
successfully.
Link: https://lore.kernel.org/linux-cxl/20240220203956.GA1502351@bhelgaas/
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
v4:
- cxl_port_dvsec() should return u16. (Lukas)
---
drivers/pci/pci.c | 45 +++++++++++++++++++++++++++++++++++
include/uapi/linux/pci_regs.h | 5 ++++
2 files changed, 50 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index e5f243dd4288..570b00fe10f7 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4927,10 +4927,55 @@ static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
}
+static u16 cxl_port_dvsec(struct pci_dev *dev)
+{
+ return pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL,
+ PCI_DVSEC_CXL_PORT);
+}
+
+static bool cxl_sbr_masked(struct pci_dev *dev)
+{
+ u16 dvsec, reg;
+ int rc;
+
+ /*
+ * No DVSEC found, either is not a CXL port, or not connected in which
+ * case mask state is a nop (CXL r3.1 sec 9.12.3 "Enumerating CXL RPs
+ * and DSPs"
+ */
+ dvsec = cxl_port_dvsec(dev);
+ if (!dvsec)
+ return false;
+
+ rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_PORT_CTL, ®);
+ if (rc || PCI_POSSIBLE_ERROR(reg))
+ return false;
+
+ /*
+ * CXL spec r3.1 8.1.5.2
+ * When 0, SBR bit in Bridge Control register of this Port has no effect.
+ * When 1, the Port shall generate hot reset when SBR bit in Bridge
+ * Control gets set to 1.
+ */
+ if (reg & PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR)
+ return false;
+
+ return true;
+}
+
static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
{
+ struct pci_dev *bridge = pci_upstream_bridge(dev);
int rc;
+ /* If it's a CXL port and the SBR control is masked, fail the SBR */
+ if (bridge && cxl_sbr_masked(bridge)) {
+ if (probe)
+ return 0;
+
+ return -ENOTTY;
+ }
+
rc = pci_dev_reset_slot_function(dev, probe);
if (rc != -ENOTTY)
return rc;
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index a39193213ff2..d61fa43662e3 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1148,4 +1148,9 @@
#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000
#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000
+/* Compute Express Link (CXL) */
+#define PCI_DVSEC_CXL_PORT 3
+#define PCI_DVSEC_CXL_PORT_CTL 0x0c
+#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001
+
#endif /* LINUX_PCI_REGS_H */
--
2.44.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v4 3/4] PCI: Create new reset method to force SBR for CXL
2024-04-09 16:01 [PATCH 0/4 v4] PCI: Add Secondary Bus Reset (SBR) support for CXL Dave Jiang
2024-04-09 16:01 ` [PATCH v4 1/4] PCI/cxl: Move PCI CXL vendor Id to a common location from CXL subsystem Dave Jiang
2024-04-09 16:01 ` [PATCH v4 2/4] PCI: Add check for CXL Secondary Bus Reset Dave Jiang
@ 2024-04-09 16:01 ` Dave Jiang
2024-04-26 19:46 ` Dan Williams
2024-04-09 16:01 ` [PATCH v4 4/4] cxl: Add post reset warning if reset results in loss of previously committed HDM decoders Dave Jiang
3 siblings, 1 reply; 15+ messages in thread
From: Dave Jiang @ 2024-04-09 16:01 UTC (permalink / raw)
To: linux-cxl, linux-pci
Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield,
Jonathan.Cameron, dave, bhelgaas, lukas
CXL spec r3.1 8.1.5.2
By default Secondary Bus Reset (SBR) is masked for CXL ports. Introduce a
new PCI reset method "cxl_bus" to force SBR on CXL ports by setting
the unmask SBR bit in the CXL DVSEC port control register before performing
the bus reset and restore the original value of the bit post reset. The
new reset method allows the user to intentionally perform SBR on a CXL
device without needing to set the "Unmask SBR" bit via a user tool.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
v4:
- Use pci_dev_lock guard() on bridge. (Dan)
---
drivers/pci/pci.c | 39 +++++++++++++++++++++++++++++++++++++++
include/linux/pci.h | 2 +-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 570b00fe10f7..3b4f7b369287 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4982,6 +4982,44 @@ static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
return pci_parent_bus_reset(dev, probe);
}
+static int cxl_reset_bus_function(struct pci_dev *dev, bool probe)
+{
+ struct pci_dev *bridge;
+ u16 dvsec, reg, val;
+ int rc;
+
+ bridge = pci_upstream_bridge(dev);
+ if (!bridge)
+ return -ENOTTY;
+
+ dvsec = cxl_port_dvsec(bridge);
+ if (!dvsec)
+ return -ENOTTY;
+
+ if (probe)
+ return 0;
+
+ guard(pci_dev)(bridge);
+ rc = pci_read_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL, ®);
+ if (rc)
+ return -ENOTTY;
+
+ if (!(reg & PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR)) {
+ val = reg | PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR;
+ pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL,
+ val);
+ } else {
+ val = reg;
+ }
+
+ rc = pci_reset_bus_function(dev, probe);
+
+ if (reg != val)
+ pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL, reg);
+
+ return rc;
+}
+
void pci_dev_lock(struct pci_dev *dev)
{
/* block PM suspend, driver probe, etc. */
@@ -5066,6 +5104,7 @@ static const struct pci_reset_fn_method pci_reset_fn_methods[] = {
{ pci_af_flr, .name = "af_flr" },
{ pci_pm_reset, .name = "pm" },
{ pci_reset_bus_function, .name = "bus" },
+ { cxl_reset_bus_function, .name = "cxl_bus" },
};
static ssize_t reset_method_show(struct device *dev,
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 16493426a04f..235f37715a43 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -51,7 +51,7 @@
PCI_STATUS_PARITY)
/* Number of reset methods used in pci_reset_fn_methods array in pci.c */
-#define PCI_NUM_RESET_METHODS 7
+#define PCI_NUM_RESET_METHODS 8
#define PCI_RESET_PROBE true
#define PCI_RESET_DO_RESET false
--
2.44.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v4 4/4] cxl: Add post reset warning if reset results in loss of previously committed HDM decoders
2024-04-09 16:01 [PATCH 0/4 v4] PCI: Add Secondary Bus Reset (SBR) support for CXL Dave Jiang
` (2 preceding siblings ...)
2024-04-09 16:01 ` [PATCH v4 3/4] PCI: Create new reset method to force SBR for CXL Dave Jiang
@ 2024-04-09 16:01 ` Dave Jiang
2024-04-26 20:03 ` Dan Williams
3 siblings, 1 reply; 15+ messages in thread
From: Dave Jiang @ 2024-04-09 16:01 UTC (permalink / raw)
To: linux-cxl, linux-pci
Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield,
Jonathan.Cameron, dave, bhelgaas, lukas
SBR is equivalent to a device been hot removed and inserted again. Doing a
SBR on a CXL type 3 device is problematic if the exported device memory is
part of system memory that cannot be offlined. The event is equivalent to
violently ripping out that range of memory from the kernel. While the
hardware requires the "Unmask SBR" bit set in the Port Control Extensions
register and the kernel currently does not unmask it, user can unmask
this bit via setpci or similar tool.
The driver does not have a way to detect whether a reset coming from the
PCI subsystem is a Function Level Reset (FLR) or SBR. The only way to
detect is to note if a decoder is marked as enabled in software but the
decoder control register indicates it's not committed.
A helper function is added to find discrepancy between the decoder
software state versus the hardware register state.
Suggested-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
v4:
- Update commit subject to clarify. (Jonathan)
---
drivers/cxl/core/pci.c | 31 +++++++++++++++++++++++++++++++
drivers/cxl/cxl.h | 2 ++
drivers/cxl/pci.c | 20 ++++++++++++++++++++
3 files changed, 53 insertions(+)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index c496a9710d62..597221f7f19b 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -1045,3 +1045,34 @@ long cxl_pci_get_latency(struct pci_dev *pdev)
return cxl_flit_size(pdev) * MEGA / bw;
}
+
+static int __cxl_endpoint_decoder_reset_detected(struct device *dev, void *data)
+{
+ struct cxl_endpoint_decoder *cxled;
+ struct cxl_port *port = data;
+ struct cxl_decoder *cxld;
+ struct cxl_hdm *cxlhdm;
+ void __iomem *hdm;
+ u32 ctrl;
+
+ if (!is_endpoint_decoder(dev))
+ return 0;
+
+ cxled = to_cxl_endpoint_decoder(dev);
+ if ((cxled->cxld.flags & CXL_DECODER_F_ENABLE) == 0)
+ return 0;
+
+ cxld = &cxled->cxld;
+ cxlhdm = dev_get_drvdata(&port->dev);
+ hdm = cxlhdm->regs.hdm_decoder;
+ ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(cxld->id));
+
+ return !FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl);
+}
+
+bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port)
+{
+ return device_for_each_child(&port->dev, port,
+ __cxl_endpoint_decoder_reset_detected);
+}
+EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, CXL);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 534e25e2f0a4..e3c237c50b59 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -895,6 +895,8 @@ void cxl_coordinates_combine(struct access_coordinate *out,
struct access_coordinate *c1,
struct access_coordinate *c2);
+bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port);
+
/*
* Unit test builds overrides this to __weak, find the 'strong' version
* of these symbols in tools/testing/cxl/.
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 110478573296..5dc1f28a031d 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -957,11 +957,31 @@ static void cxl_error_resume(struct pci_dev *pdev)
dev->driver ? "successful" : "failed");
}
+static void cxl_reset_done(struct pci_dev *pdev)
+{
+ struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
+ struct cxl_memdev *cxlmd = cxlds->cxlmd;
+ struct device *dev = &pdev->dev;
+
+ /*
+ * FLR does not expect to touch the HDM decoders and related registers.
+ * SBR however will wipe all device configurations.
+ * Issue warning if there was active decoder before reset that no
+ * longer exists.
+ */
+ if (cxl_endpoint_decoder_reset_detected(cxlmd->endpoint)) {
+ dev_warn(dev, "SBR happened without memory regions removal.\n");
+ dev_warn(dev, "System may be unstable if regions hosted system memory.\n");
+ add_taint(TAINT_USER, LOCKDEP_NOW_UNRELIABLE);
+ }
+}
+
static const struct pci_error_handlers cxl_error_handlers = {
.error_detected = cxl_error_detected,
.slot_reset = cxl_slot_reset,
.resume = cxl_error_resume,
.cor_error_detected = cxl_cor_error_detected,
+ .reset_done = cxl_reset_done,
};
static struct pci_driver cxl_pci_driver = {
--
2.44.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v4 1/4] PCI/cxl: Move PCI CXL vendor Id to a common location from CXL subsystem
2024-04-09 16:01 ` [PATCH v4 1/4] PCI/cxl: Move PCI CXL vendor Id to a common location from CXL subsystem Dave Jiang
@ 2024-04-09 21:28 ` Kuppuswamy Sathyanarayanan
2024-04-09 22:51 ` Dan Williams
1 sibling, 0 replies; 15+ messages in thread
From: Kuppuswamy Sathyanarayanan @ 2024-04-09 21:28 UTC (permalink / raw)
To: Dave Jiang, linux-cxl, linux-pci
Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield,
Jonathan.Cameron, dave, bhelgaas, lukas, Bjorn Helgaas
On 4/9/24 9:01 AM, Dave Jiang wrote:
> Move PCI_DVSEC_VENDOR_ID_CXL in CXL private code to PCI_VENDOR_ID_CXL in
> pci_ids.h in order to be utilized in PCI subsystem.
>
> The response Bjorn received from the PCI SIG was "1E98h is not a VID in our
> system, but 1E98 has already been reserved by CXL." He suggested "we should
> add '#define PCI_VENDOR_ID_CXL 0x1e98' so that if we ever *do* see such an
> assignment, we'll be more likely to flag it as an issue.
Nit: Instead of including the comments as-it-is, I think it is better just state
the conclusion.
>
> Link: https://lore.kernel.org/linux-cxl/20240402172323.GA1818777@bhelgaas/
> Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> ---
> drivers/cxl/core/pci.c | 6 +++---
> drivers/cxl/core/regs.c | 2 +-
> drivers/cxl/cxlpci.h | 1 -
> drivers/cxl/pci.c | 2 +-
> drivers/perf/cxl_pmu.c | 2 +-
> include/linux/pci_ids.h | 2 ++
> 6 files changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 0df09bd79408..c496a9710d62 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -525,7 +525,7 @@ static int cxl_cdat_get_length(struct device *dev,
> __le32 response[2];
> int rc;
>
> - rc = pci_doe(doe_mb, PCI_DVSEC_VENDOR_ID_CXL,
> + rc = pci_doe(doe_mb, PCI_VENDOR_ID_CXL,
> CXL_DOE_PROTOCOL_TABLE_ACCESS,
> &request, sizeof(request),
> &response, sizeof(response));
> @@ -555,7 +555,7 @@ static int cxl_cdat_read_table(struct device *dev,
> __le32 request = CDAT_DOE_REQ(entry_handle);
> int rc;
>
> - rc = pci_doe(doe_mb, PCI_DVSEC_VENDOR_ID_CXL,
> + rc = pci_doe(doe_mb, PCI_VENDOR_ID_CXL,
> CXL_DOE_PROTOCOL_TABLE_ACCESS,
> &request, sizeof(request),
> rsp, sizeof(*rsp) + remaining);
> @@ -640,7 +640,7 @@ void read_cdat_data(struct cxl_port *port)
> if (!pdev)
> return;
>
> - doe_mb = pci_find_doe_mailbox(pdev, PCI_DVSEC_VENDOR_ID_CXL,
> + doe_mb = pci_find_doe_mailbox(pdev, PCI_VENDOR_ID_CXL,
> CXL_DOE_PROTOCOL_TABLE_ACCESS);
> if (!doe_mb) {
> dev_dbg(dev, "No CDAT mailbox\n");
> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index 372786f80955..da52fc9e234b 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -313,7 +313,7 @@ int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type,
> .resource = CXL_RESOURCE_NONE,
> };
>
> - regloc = pci_find_dvsec_capability(pdev, PCI_DVSEC_VENDOR_ID_CXL,
> + regloc = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
> CXL_DVSEC_REG_LOCATOR);
> if (!regloc)
> return -ENXIO;
> diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
> index 93992a1c8eec..4da07727ab9c 100644
> --- a/drivers/cxl/cxlpci.h
> +++ b/drivers/cxl/cxlpci.h
> @@ -13,7 +13,6 @@
> * "DVSEC" redundancies removed. When obvious, abbreviations may be used.
> */
> #define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20)
> -#define PCI_DVSEC_VENDOR_ID_CXL 0x1E98
>
> /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
> #define CXL_DVSEC_PCIE_DEVICE 0
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 2ff361e756d6..110478573296 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -817,7 +817,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> cxlds->rcd = is_cxl_restricted(pdev);
> cxlds->serial = pci_get_dsn(pdev);
> cxlds->cxl_dvsec = pci_find_dvsec_capability(
> - pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE);
> + pdev, PCI_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE);
> if (!cxlds->cxl_dvsec)
> dev_warn(&pdev->dev,
> "Device DVSEC not present, skip CXL.mem init\n");
> diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c
> index 308c9969642e..a1b742b1a735 100644
> --- a/drivers/perf/cxl_pmu.c
> +++ b/drivers/perf/cxl_pmu.c
> @@ -345,7 +345,7 @@ static ssize_t cxl_pmu_event_sysfs_show(struct device *dev,
>
> /* For CXL spec defined events */
> #define CXL_PMU_EVENT_CXL_ATTR(_name, _gid, _msk) \
> - CXL_PMU_EVENT_ATTR(_name, PCI_DVSEC_VENDOR_ID_CXL, _gid, _msk)
> + CXL_PMU_EVENT_ATTR(_name, PCI_VENDOR_ID_CXL, _gid, _msk)
>
> static struct attribute *cxl_pmu_event_attrs[] = {
> CXL_PMU_EVENT_CXL_ATTR(clock_ticks, CXL_PMU_GID_CLOCK_TICKS, BIT(0)),
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index a0c75e467df3..7dfbf6d96b3d 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -2607,6 +2607,8 @@
>
> #define PCI_VENDOR_ID_ALIBABA 0x1ded
>
> +#define PCI_VENDOR_ID_CXL 0x1e98
> +
> #define PCI_VENDOR_ID_TEHUTI 0x1fc9
> #define PCI_DEVICE_ID_TEHUTI_3009 0x3009
> #define PCI_DEVICE_ID_TEHUTI_3010 0x3010
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4 2/4] PCI: Add check for CXL Secondary Bus Reset
2024-04-09 16:01 ` [PATCH v4 2/4] PCI: Add check for CXL Secondary Bus Reset Dave Jiang
@ 2024-04-09 21:39 ` Kuppuswamy Sathyanarayanan
2024-04-09 21:56 ` Dave Jiang
2024-04-09 22:56 ` Dan Williams
1 sibling, 1 reply; 15+ messages in thread
From: Kuppuswamy Sathyanarayanan @ 2024-04-09 21:39 UTC (permalink / raw)
To: Dave Jiang, linux-cxl, linux-pci
Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield,
Jonathan.Cameron, dave, bhelgaas, lukas
On 4/9/24 9:01 AM, Dave Jiang wrote:
> Per CXL spec r3.1 8.1.5.2, Secondary Bus Reset (SBR) is masked unless the
> "Unmask SBR" bit is set. Add a check to the PCI secondary bus reset
> path to fail the CXL SBR request if the "Unmask SBR" bit is clear in
> the CXL Port Control Extensions register by returning -ENOTTY.
>
> When the "Unmask SBR" bit is set to 0 (default), the bus_reset would
> appear to have executed successfully. However the operation is actually
> masked. The intention is to inform the user that SBR for the CXL device
> is masked and will not go through.
>
> If the "Unmask SBR" bit is set to 1, then the bus reset will execute
> successfully.
>
> Link: https://lore.kernel.org/linux-cxl/20240220203956.GA1502351@bhelgaas/
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
> v4:
> - cxl_port_dvsec() should return u16. (Lukas)
> ---
> drivers/pci/pci.c | 45 +++++++++++++++++++++++++++++++++++
> include/uapi/linux/pci_regs.h | 5 ++++
> 2 files changed, 50 insertions(+)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index e5f243dd4288..570b00fe10f7 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -4927,10 +4927,55 @@ static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
> return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
> }
>
> +static u16 cxl_port_dvsec(struct pci_dev *dev)
> +{
> + return pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL,
> + PCI_DVSEC_CXL_PORT);
> +}
Since cxl_sbr_masked() is the only user of this function, why not directly
check for this capability there.
> +
> +static bool cxl_sbr_masked(struct pci_dev *dev)
> +{
> + u16 dvsec, reg;
> + int rc;
> +
> + /*
> + * No DVSEC found, either is not a CXL port, or not connected in which
> + * case mask state is a nop (CXL r3.1 sec 9.12.3 "Enumerating CXL RPs
> + * and DSPs"
> + */
> + dvsec = cxl_port_dvsec(dev);
> + if (!dvsec)
> + return false;
> +
> + rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_PORT_CTL, ®);
> + if (rc || PCI_POSSIBLE_ERROR(reg))
> + return false;
> +
> + /*
> + * CXL spec r3.1 8.1.5.2
> + * When 0, SBR bit in Bridge Control register of this Port has no effect.
> + * When 1, the Port shall generate hot reset when SBR bit in Bridge
> + * Control gets set to 1.
> + */
> + if (reg & PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR)
> + return false;
> +
> + return true;
> +}
> +
> static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
> {
> + struct pci_dev *bridge = pci_upstream_bridge(dev);
> int rc;
>
> + /* If it's a CXL port and the SBR control is masked, fail the SBR */
> + if (bridge && cxl_sbr_masked(bridge)) {
> + if (probe)
> + return 0;
Why return success during the probe?
> +
> + return -ENOTTY;
> + }
> +
> rc = pci_dev_reset_slot_function(dev, probe);
> if (rc != -ENOTTY)
> return rc;
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index a39193213ff2..d61fa43662e3 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -1148,4 +1148,9 @@
> #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000
> #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000
>
> +/* Compute Express Link (CXL) */
> +#define PCI_DVSEC_CXL_PORT 3
> +#define PCI_DVSEC_CXL_PORT_CTL 0x0c
> +#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001
> +
> #endif /* LINUX_PCI_REGS_H */
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4 2/4] PCI: Add check for CXL Secondary Bus Reset
2024-04-09 21:39 ` Kuppuswamy Sathyanarayanan
@ 2024-04-09 21:56 ` Dave Jiang
2024-04-11 2:33 ` Kuppuswamy Sathyanarayanan
0 siblings, 1 reply; 15+ messages in thread
From: Dave Jiang @ 2024-04-09 21:56 UTC (permalink / raw)
To: Kuppuswamy Sathyanarayanan, linux-cxl, linux-pci
Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield,
Jonathan.Cameron, dave, bhelgaas, lukas
On 4/9/24 2:39 PM, Kuppuswamy Sathyanarayanan wrote:
>
> On 4/9/24 9:01 AM, Dave Jiang wrote:
>> Per CXL spec r3.1 8.1.5.2, Secondary Bus Reset (SBR) is masked unless the
>> "Unmask SBR" bit is set. Add a check to the PCI secondary bus reset
>> path to fail the CXL SBR request if the "Unmask SBR" bit is clear in
>> the CXL Port Control Extensions register by returning -ENOTTY.
>>
>> When the "Unmask SBR" bit is set to 0 (default), the bus_reset would
>> appear to have executed successfully. However the operation is actually
>> masked. The intention is to inform the user that SBR for the CXL device
>> is masked and will not go through.
>>
>> If the "Unmask SBR" bit is set to 1, then the bus reset will execute
>> successfully.
>>
>> Link: https://lore.kernel.org/linux-cxl/20240220203956.GA1502351@bhelgaas/
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>> ---
>> v4:
>> - cxl_port_dvsec() should return u16. (Lukas)
>> ---
>> drivers/pci/pci.c | 45 +++++++++++++++++++++++++++++++++++
>> include/uapi/linux/pci_regs.h | 5 ++++
>> 2 files changed, 50 insertions(+)
>>
>> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
>> index e5f243dd4288..570b00fe10f7 100644
>> --- a/drivers/pci/pci.c
>> +++ b/drivers/pci/pci.c
>> @@ -4927,10 +4927,55 @@ static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
>> return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
>> }
>>
>> +static u16 cxl_port_dvsec(struct pci_dev *dev)
>> +{
>> + return pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL,
>> + PCI_DVSEC_CXL_PORT);
>> +}
>
> Since cxl_sbr_masked() is the only user of this function, why not directly
> check for this capability there.
It's used by another function in the 3rd patch. I previously had it open coded. But Dan said to reduce churn, just create the function to begin with instead of moving that code to a function later on.
>
>> +
>> +static bool cxl_sbr_masked(struct pci_dev *dev)
>> +{
>> + u16 dvsec, reg;
>> + int rc;
>> +
>> + /*
>> + * No DVSEC found, either is not a CXL port, or not connected in which
>> + * case mask state is a nop (CXL r3.1 sec 9.12.3 "Enumerating CXL RPs
>> + * and DSPs"
>> + */
>> + dvsec = cxl_port_dvsec(dev);
>> + if (!dvsec)
>> + return false;
>> +
>> + rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_PORT_CTL, ®);
>> + if (rc || PCI_POSSIBLE_ERROR(reg))
>> + return false;
>> +
>> + /*
>> + * CXL spec r3.1 8.1.5.2
>> + * When 0, SBR bit in Bridge Control register of this Port has no effect.
>> + * When 1, the Port shall generate hot reset when SBR bit in Bridge
>> + * Control gets set to 1.
>> + */
>> + if (reg & PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR)
>> + return false;
>> +
>> + return true;
>> +}
>> +
>> static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
>> {
>> + struct pci_dev *bridge = pci_upstream_bridge(dev);
>> int rc;
>>
>> + /* If it's a CXL port and the SBR control is masked, fail the SBR */
>> + if (bridge && cxl_sbr_masked(bridge)) {
>> + if (probe)
>> + return 0;
>
> Why return success during the probe?
Otherwise the reset_method will disappear as available after initial probe. We want to leave the reset method available. If the register bit gets unmasked we can perform a bus reset. We don't want to take it away the option entirely if it's masked.
>
>> +
>> + return -ENOTTY;
>> + }
>> +
>> rc = pci_dev_reset_slot_function(dev, probe);
>> if (rc != -ENOTTY)
>> return rc;
>> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
>> index a39193213ff2..d61fa43662e3 100644
>> --- a/include/uapi/linux/pci_regs.h
>> +++ b/include/uapi/linux/pci_regs.h
>> @@ -1148,4 +1148,9 @@
>> #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000
>> #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000
>>
>> +/* Compute Express Link (CXL) */
>> +#define PCI_DVSEC_CXL_PORT 3
>> +#define PCI_DVSEC_CXL_PORT_CTL 0x0c
>> +#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001
>> +
>> #endif /* LINUX_PCI_REGS_H */
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4 1/4] PCI/cxl: Move PCI CXL vendor Id to a common location from CXL subsystem
2024-04-09 16:01 ` [PATCH v4 1/4] PCI/cxl: Move PCI CXL vendor Id to a common location from CXL subsystem Dave Jiang
2024-04-09 21:28 ` Kuppuswamy Sathyanarayanan
@ 2024-04-09 22:51 ` Dan Williams
1 sibling, 0 replies; 15+ messages in thread
From: Dan Williams @ 2024-04-09 22:51 UTC (permalink / raw)
To: Dave Jiang, linux-cxl, linux-pci
Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield,
Jonathan.Cameron, dave, bhelgaas, lukas, Bjorn Helgaas
Dave Jiang wrote:
> Move PCI_DVSEC_VENDOR_ID_CXL in CXL private code to PCI_VENDOR_ID_CXL in
> pci_ids.h in order to be utilized in PCI subsystem.
>
> The response Bjorn received from the PCI SIG was "1E98h is not a VID in our
> system, but 1E98 has already been reserved by CXL." He suggested "we should
> add '#define PCI_VENDOR_ID_CXL 0x1e98' so that if we ever *do* see such an
> assignment, we'll be more likely to flag it as an issue.
Perhaps indent these as quotes, the second quote is missing a trailing
double-quote.
...but maybe even better to justify this change rather than the reaction
to the change. Something like:
--
When uplevelling PCI_DVSEC_VENDOR_ID_CXL to a common location Bjorn
suggested making it a proper PCI_VENDOR_ID_* define in
include/linux/pci_ids.h. While it is not in the PCI IDs database it is a
reserved value and Linux treats it as a 'vendor id' for all intents and
purposes [1].
---
...where that footnote can link back to the conversation for the
background.
Other than that, you can add:
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4 2/4] PCI: Add check for CXL Secondary Bus Reset
2024-04-09 16:01 ` [PATCH v4 2/4] PCI: Add check for CXL Secondary Bus Reset Dave Jiang
2024-04-09 21:39 ` Kuppuswamy Sathyanarayanan
@ 2024-04-09 22:56 ` Dan Williams
1 sibling, 0 replies; 15+ messages in thread
From: Dan Williams @ 2024-04-09 22:56 UTC (permalink / raw)
To: Dave Jiang, linux-cxl, linux-pci
Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield,
Jonathan.Cameron, dave, bhelgaas, lukas
Dave Jiang wrote:
> Per CXL spec r3.1 8.1.5.2, Secondary Bus Reset (SBR) is masked unless the
> "Unmask SBR" bit is set. Add a check to the PCI secondary bus reset
> path to fail the CXL SBR request if the "Unmask SBR" bit is clear in
> the CXL Port Control Extensions register by returning -ENOTTY.
>
> When the "Unmask SBR" bit is set to 0 (default), the bus_reset would
Feels like a missing "Otherwise," at the beginning of this sentence to
indicate transition from what the patch does to what happens without the
patch.
> appear to have executed successfully. However the operation is actually
> masked. The intention is to inform the user that SBR for the CXL device
> is masked and will not go through.
>
> If the "Unmask SBR" bit is set to 1, then the bus reset will execute
> successfully.
Otherwise, heh heh heh, you can add:
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
...I would say, do not spin the patch just for that small fixup.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4 2/4] PCI: Add check for CXL Secondary Bus Reset
2024-04-09 21:56 ` Dave Jiang
@ 2024-04-11 2:33 ` Kuppuswamy Sathyanarayanan
0 siblings, 0 replies; 15+ messages in thread
From: Kuppuswamy Sathyanarayanan @ 2024-04-11 2:33 UTC (permalink / raw)
To: Dave Jiang, linux-cxl, linux-pci
Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield,
Jonathan.Cameron, dave, bhelgaas, lukas
On 4/9/24 2:56 PM, Dave Jiang wrote:
>
> On 4/9/24 2:39 PM, Kuppuswamy Sathyanarayanan wrote:
>> On 4/9/24 9:01 AM, Dave Jiang wrote:
>>> Per CXL spec r3.1 8.1.5.2, Secondary Bus Reset (SBR) is masked unless the
>>> "Unmask SBR" bit is set. Add a check to the PCI secondary bus reset
>>> path to fail the CXL SBR request if the "Unmask SBR" bit is clear in
>>> the CXL Port Control Extensions register by returning -ENOTTY.
>>>
>>> When the "Unmask SBR" bit is set to 0 (default), the bus_reset would
>>> appear to have executed successfully. However the operation is actually
>>> masked. The intention is to inform the user that SBR for the CXL device
>>> is masked and will not go through.
>>>
>>> If the "Unmask SBR" bit is set to 1, then the bus reset will execute
>>> successfully.
>>>
>>> Link: https://lore.kernel.org/linux-cxl/20240220203956.GA1502351@bhelgaas/
>>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>>> ---
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
>>> v4:
>>> - cxl_port_dvsec() should return u16. (Lukas)
>>> ---
>>> drivers/pci/pci.c | 45 +++++++++++++++++++++++++++++++++++
>>> include/uapi/linux/pci_regs.h | 5 ++++
>>> 2 files changed, 50 insertions(+)
>>>
>>> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
>>> index e5f243dd4288..570b00fe10f7 100644
>>> --- a/drivers/pci/pci.c
>>> +++ b/drivers/pci/pci.c
>>> @@ -4927,10 +4927,55 @@ static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
>>> return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
>>> }
>>>
>>> +static u16 cxl_port_dvsec(struct pci_dev *dev)
>>> +{
>>> + return pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL,
>>> + PCI_DVSEC_CXL_PORT);
>>> +}
>> Since cxl_sbr_masked() is the only user of this function, why not directly
>> check for this capability there.
> It's used by another function in the 3rd patch. I previously had it open coded. But Dan said to reduce churn, just create the function to begin with instead of moving that code to a function later on.
May be that patch would be the right place to introduce a helper function. But I think it fine either way.
>>> +
>>> +static bool cxl_sbr_masked(struct pci_dev *dev)
>>> +{
>>> + u16 dvsec, reg;
>>> + int rc;
>>> +
>>> + /*
>>> + * No DVSEC found, either is not a CXL port, or not connected in which
>>> + * case mask state is a nop (CXL r3.1 sec 9.12.3 "Enumerating CXL RPs
>>> + * and DSPs"
>>> + */
>>> + dvsec = cxl_port_dvsec(dev);
>>> + if (!dvsec)
>>> + return false;
>>> +
>>> + rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_PORT_CTL, ®);
>>> + if (rc || PCI_POSSIBLE_ERROR(reg))
>>> + return false;
>>> +
>>> + /*
>>> + * CXL spec r3.1 8.1.5.2
>>> + * When 0, SBR bit in Bridge Control register of this Port has no effect.
>>> + * When 1, the Port shall generate hot reset when SBR bit in Bridge
>>> + * Control gets set to 1.
>>> + */
>>> + if (reg & PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR)
>>> + return false;
>>> +
>>> + return true;
>>> +}
>>> +
>>> static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
>>> {
>>> + struct pci_dev *bridge = pci_upstream_bridge(dev);
>>> int rc;
>>>
>>> + /* If it's a CXL port and the SBR control is masked, fail the SBR */
>>> + if (bridge && cxl_sbr_masked(bridge)) {
>>> + if (probe)
>>> + return 0;
>> Why return success during the probe?
> Otherwise the reset_method will disappear as available after initial probe. We want to leave the reset method available. If the register bit gets unmasked we can perform a bus reset. We don't want to take it away the option entirely if it's masked.
Ok.
>>> +
>>> + return -ENOTTY;
>>> + }
>>> +
>>> rc = pci_dev_reset_slot_function(dev, probe);
>>> if (rc != -ENOTTY)
>>> return rc;
>>> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
>>> index a39193213ff2..d61fa43662e3 100644
>>> --- a/include/uapi/linux/pci_regs.h
>>> +++ b/include/uapi/linux/pci_regs.h
>>> @@ -1148,4 +1148,9 @@
>>> #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000
>>> #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000
>>>
>>> +/* Compute Express Link (CXL) */
>>> +#define PCI_DVSEC_CXL_PORT 3
>>> +#define PCI_DVSEC_CXL_PORT_CTL 0x0c
>>> +#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001
>>> +
>>> #endif /* LINUX_PCI_REGS_H */
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4 3/4] PCI: Create new reset method to force SBR for CXL
2024-04-09 16:01 ` [PATCH v4 3/4] PCI: Create new reset method to force SBR for CXL Dave Jiang
@ 2024-04-26 19:46 ` Dan Williams
2024-04-27 6:19 ` Lukas Wunner
0 siblings, 1 reply; 15+ messages in thread
From: Dan Williams @ 2024-04-26 19:46 UTC (permalink / raw)
To: Dave Jiang, linux-cxl, linux-pci
Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield,
Jonathan.Cameron, dave, bhelgaas, lukas
Dave Jiang wrote:
> CXL spec r3.1 8.1.5.2
> By default Secondary Bus Reset (SBR) is masked for CXL ports. Introduce a
> new PCI reset method "cxl_bus" to force SBR on CXL ports by setting
> the unmask SBR bit in the CXL DVSEC port control register before performing
> the bus reset and restore the original value of the bit post reset. The
> new reset method allows the user to intentionally perform SBR on a CXL
> device without needing to set the "Unmask SBR" bit via a user tool.
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
> v4:
> - Use pci_dev_lock guard() on bridge. (Dan)
> ---
> drivers/pci/pci.c | 39 +++++++++++++++++++++++++++++++++++++++
> include/linux/pci.h | 2 +-
> 2 files changed, 40 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 570b00fe10f7..3b4f7b369287 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -4982,6 +4982,44 @@ static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
> return pci_parent_bus_reset(dev, probe);
> }
>
> +static int cxl_reset_bus_function(struct pci_dev *dev, bool probe)
> +{
> + struct pci_dev *bridge;
> + u16 dvsec, reg, val;
> + int rc;
> +
> + bridge = pci_upstream_bridge(dev);
> + if (!bridge)
> + return -ENOTTY;
> +
> + dvsec = cxl_port_dvsec(bridge);
> + if (!dvsec)
> + return -ENOTTY;
> +
> + if (probe)
> + return 0;
> +
> + guard(pci_dev)(bridge);
My concern here is this sets up a pci_reset_function() locking order of:
pci_dev_lock(@dev)
pci_dev_lock(pci_upstream_bridge(@dev))
Compare that to pci_reset_bus() that does:
pci_dev_lock(pci_upstream_bridge(@dev))
pci_dev_lock(@dev)
This also highlights that the pci_dev_lock() performed by
pci_reset_function() has long been insufficient for the
pci_reset_bus_function() method case that could race userspace when
pci_reset_secondary_bus() is manipulating the bridge control register.
So, if the goal of the lock is to prevent userspace from clobbering the
kernel's read-modify-write cycles of @dev's parent bridge, then the lock
needs to be held over both the cxl_reset_bus_function() and the
pci_reset_bus_function() cases, and it needs to be taken in
upstream-bridge => endpoint order.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4 4/4] cxl: Add post reset warning if reset results in loss of previously committed HDM decoders
2024-04-09 16:01 ` [PATCH v4 4/4] cxl: Add post reset warning if reset results in loss of previously committed HDM decoders Dave Jiang
@ 2024-04-26 20:03 ` Dan Williams
0 siblings, 0 replies; 15+ messages in thread
From: Dan Williams @ 2024-04-26 20:03 UTC (permalink / raw)
To: Dave Jiang, linux-cxl, linux-pci
Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield,
Jonathan.Cameron, dave, bhelgaas, lukas
Dave Jiang wrote:
> SBR is equivalent to a device been hot removed and inserted again. Doing a
> SBR on a CXL type 3 device is problematic if the exported device memory is
> part of system memory that cannot be offlined. The event is equivalent to
> violently ripping out that range of memory from the kernel. While the
> hardware requires the "Unmask SBR" bit set in the Port Control Extensions
> register and the kernel currently does not unmask it, user can unmask
> this bit via setpci or similar tool.
>
> The driver does not have a way to detect whether a reset coming from the
> PCI subsystem is a Function Level Reset (FLR) or SBR. The only way to
> detect is to note if a decoder is marked as enabled in software but the
> decoder control register indicates it's not committed.
>
> A helper function is added to find discrepancy between the decoder
> software state versus the hardware register state.
>
> Suggested-by: Dan Williams <dan.j.williams@intel.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
> v4:
> - Update commit subject to clarify. (Jonathan)
> ---
> drivers/cxl/core/pci.c | 31 +++++++++++++++++++++++++++++++
> drivers/cxl/cxl.h | 2 ++
> drivers/cxl/pci.c | 20 ++++++++++++++++++++
> 3 files changed, 53 insertions(+)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index c496a9710d62..597221f7f19b 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -1045,3 +1045,34 @@ long cxl_pci_get_latency(struct pci_dev *pdev)
>
> return cxl_flit_size(pdev) * MEGA / bw;
> }
> +
> +static int __cxl_endpoint_decoder_reset_detected(struct device *dev, void *data)
> +{
> + struct cxl_endpoint_decoder *cxled;
> + struct cxl_port *port = data;
> + struct cxl_decoder *cxld;
> + struct cxl_hdm *cxlhdm;
> + void __iomem *hdm;
> + u32 ctrl;
> +
> + if (!is_endpoint_decoder(dev))
> + return 0;
> +
> + cxled = to_cxl_endpoint_decoder(dev);
> + if ((cxled->cxld.flags & CXL_DECODER_F_ENABLE) == 0)
> + return 0;
> +
> + cxld = &cxled->cxld;
Nit, if this code is going to use the shortened @cxld, then use it above
too, i.e.:
cxld = &cxled->cxld;
if ((cxld->flags & CXL_DECODER_F_ENABLE) == 0)
return 0;
...in fact, since only the base 'struct cxl_decoder' fields are needed
just go straight to:
cxld = to_cxl_decoder(dev);
> + cxlhdm = dev_get_drvdata(&port->dev);
> + hdm = cxlhdm->regs.hdm_decoder;
> + ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(cxld->id));
> +
> + return !FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl);
> +}
> +
> +bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port)
> +{
> + return device_for_each_child(&port->dev, port,
> + __cxl_endpoint_decoder_reset_detected);
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, CXL);
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 534e25e2f0a4..e3c237c50b59 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -895,6 +895,8 @@ void cxl_coordinates_combine(struct access_coordinate *out,
> struct access_coordinate *c1,
> struct access_coordinate *c2);
>
> +bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port);
> +
> /*
> * Unit test builds overrides this to __weak, find the 'strong' version
> * of these symbols in tools/testing/cxl/.
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 110478573296..5dc1f28a031d 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -957,11 +957,31 @@ static void cxl_error_resume(struct pci_dev *pdev)
> dev->driver ? "successful" : "failed");
> }
>
> +static void cxl_reset_done(struct pci_dev *pdev)
> +{
> + struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
> + struct cxl_memdev *cxlmd = cxlds->cxlmd;
> + struct device *dev = &pdev->dev;
> +
> + /*
> + * FLR does not expect to touch the HDM decoders and related registers.
> + * SBR however will wipe all device configurations.
> + * Issue warning if there was active decoder before reset that no
> + * longer exists.
> + */
> + if (cxl_endpoint_decoder_reset_detected(cxlmd->endpoint)) {
This needs to be careful about racing disabled cxlmd, something like:
guard(device)(&cxlmd->dev);
if (cxlmd->endpoint && cxl_endpoint_decoder_reset_detected(cxlmd->endpoint)
> + dev_warn(dev, "SBR happened without memory regions removal.\n");
> + dev_warn(dev, "System may be unstable if regions hosted system memory.\n");
These should probably be higher than warn, dev_crit() is likely
appropriate.
> + add_taint(TAINT_USER, LOCKDEP_NOW_UNRELIABLE);
I see no reason to assert that lockdep needs to be turned off. Likely
the kernel is crashing before even getting to this point, but if it
survives lockdep is probably ok.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4 3/4] PCI: Create new reset method to force SBR for CXL
2024-04-26 19:46 ` Dan Williams
@ 2024-04-27 6:19 ` Lukas Wunner
2024-04-27 17:07 ` Dan Williams
0 siblings, 1 reply; 15+ messages in thread
From: Lukas Wunner @ 2024-04-27 6:19 UTC (permalink / raw)
To: Dan Williams
Cc: Dave Jiang, linux-cxl, linux-pci, ira.weiny, vishal.l.verma,
alison.schofield, Jonathan.Cameron, dave, bhelgaas
On Fri, Apr 26, 2024 at 12:46:45PM -0700, Dan Williams wrote:
> This also highlights that the pci_dev_lock() performed by
> pci_reset_function() has long been insufficient for the
> pci_reset_bus_function() method case that could race userspace when
> pci_reset_secondary_bus() is manipulating the bridge control register.
>
> So, if the goal of the lock is to prevent userspace from clobbering the
> kernel's read-modify-write cycles of @dev's parent bridge, then the lock
> needs to be held over both the cxl_reset_bus_function() and the
> pci_reset_bus_function() cases, and it needs to be taken in
> upstream-bridge => endpoint order.
No, the device lock is taken to prevent the driver from unbinding.
It has nothing to do with protecting RMW of parent bridge registers.
Here's Christoph Hellwig's explanation why he introduced acquisition
of the device lock in the PCI reset code paths:
https://lore.kernel.org/all/20200325104018.GA30853@lst.de/
TL;DR: The PCI core calls the driver's ->reset_prepare and ->reset_done
callbacks and the driver needs to be held in place for that.
Thanks,
Lukas
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4 3/4] PCI: Create new reset method to force SBR for CXL
2024-04-27 6:19 ` Lukas Wunner
@ 2024-04-27 17:07 ` Dan Williams
0 siblings, 0 replies; 15+ messages in thread
From: Dan Williams @ 2024-04-27 17:07 UTC (permalink / raw)
To: Lukas Wunner, Dan Williams
Cc: Dave Jiang, linux-cxl, linux-pci, ira.weiny, vishal.l.verma,
alison.schofield, Jonathan.Cameron, dave, bhelgaas
Lukas Wunner wrote:
> On Fri, Apr 26, 2024 at 12:46:45PM -0700, Dan Williams wrote:
> > This also highlights that the pci_dev_lock() performed by
> > pci_reset_function() has long been insufficient for the
> > pci_reset_bus_function() method case that could race userspace when
> > pci_reset_secondary_bus() is manipulating the bridge control register.
> >
> > So, if the goal of the lock is to prevent userspace from clobbering the
> > kernel's read-modify-write cycles of @dev's parent bridge, then the lock
> > needs to be held over both the cxl_reset_bus_function() and the
> > pci_reset_bus_function() cases, and it needs to be taken in
> > upstream-bridge => endpoint order.
>
> No, the device lock is taken to prevent the driver from unbinding.
> It has nothing to do with protecting RMW of parent bridge registers.
>
> Here's Christoph Hellwig's explanation why he introduced acquisition
> of the device lock in the PCI reset code paths:
>
> https://lore.kernel.org/all/20200325104018.GA30853@lst.de/
>
> TL;DR: The PCI core calls the driver's ->reset_prepare and ->reset_done
> callbacks and the driver needs to be held in place for that.
Yes, that's what device_lock() is for, *but* that's not what
pci_cfg_access_lock() is for.
So when I say that pci_dev_lock() is to protect read-modify-write
configuration cycle access of an endpoint to be reset, I am talking
about pci_cfg_access_lock() not device_lock(). For better or worse
pci_dev_lock() does both, and maybe device_lock() should be open-coded
separately.
So there is a discrepancy when it comes to protecting manipulation of
secondary bus reset control registers of a bridge. The
pci_cfg_access_lock() protection is applied to the bridge in the
pci_reset_bus() case, but not the pci_reset_bus_function() case.
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2024-04-27 17:07 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-04-09 16:01 [PATCH 0/4 v4] PCI: Add Secondary Bus Reset (SBR) support for CXL Dave Jiang
2024-04-09 16:01 ` [PATCH v4 1/4] PCI/cxl: Move PCI CXL vendor Id to a common location from CXL subsystem Dave Jiang
2024-04-09 21:28 ` Kuppuswamy Sathyanarayanan
2024-04-09 22:51 ` Dan Williams
2024-04-09 16:01 ` [PATCH v4 2/4] PCI: Add check for CXL Secondary Bus Reset Dave Jiang
2024-04-09 21:39 ` Kuppuswamy Sathyanarayanan
2024-04-09 21:56 ` Dave Jiang
2024-04-11 2:33 ` Kuppuswamy Sathyanarayanan
2024-04-09 22:56 ` Dan Williams
2024-04-09 16:01 ` [PATCH v4 3/4] PCI: Create new reset method to force SBR for CXL Dave Jiang
2024-04-26 19:46 ` Dan Williams
2024-04-27 6:19 ` Lukas Wunner
2024-04-27 17:07 ` Dan Williams
2024-04-09 16:01 ` [PATCH v4 4/4] cxl: Add post reset warning if reset results in loss of previously committed HDM decoders Dave Jiang
2024-04-26 20:03 ` Dan Williams
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