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From: "Wells Lu 呂芳騰" <wells.lu@sunplus.com>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Wells Lu <wellslutw@gmail.com>,
	Linus Walleij <linus.walleij@linaro.org>,
	"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	devicetree <devicetree@vger.kernel.org>,
	linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>,
	"dvorkin@tibbo.com" <dvorkin@tibbo.com>
Subject: RE: [PATCH v5 2/2] pinctrl: Add driver for Sunplus SP7021
Date: Fri, 14 Jan 2022 10:56:10 +0000	[thread overview]
Message-ID: <b9c1876c9d0f48a3a8d7e091d47fc069@sphcmbx02.sunplus.com.tw> (raw)
In-Reply-To: <CAHp75VfxtGue7bbMm_MU2GWwWo4aZLW2Pj_U9ocCQmWr6wfGMw@mail.gmail.com>

> ...
> 
> > > > > > > > +       bool "Sunplus SP7021 PinMux and GPIO driver"
> > > > > > >
> > > > > > > Why bool and not tristate?
> > > > > >
> > > > > > Pinctrl driver is selected by many drivers in SP7021 platform.
> > > > > > We never build it as a module, but build-in to kernel.
> > > > > > So we use "bool".
> > > > > >
> > > > > > Should we set it to tristate?
> > > > >
> > > > > You still haven't answered "why", so I can't tell you.
> > > >
> > > > I am puzzled because I think I have answered "why".
> > >
> > > Nope. :-)
> > >
> > > > Because Pinctrl driver is necessary for all SP7021-based platforms.
> > >
> > > "Why?" Why is it necessary (to be built-in)?
> >
> > Pinctrl is necessary to be built-in because drivers of boot-device,
> > like eMMC, SD card, NAND flash, and NOR flash drivers, need it.
> >
> > SP7021 supports booting from eMMC, SD card, NAND flash and NOR flash
> > devices. Their drivers need Pinctrl driver probes in advance.
> 
> On x86 platforms, for example, booting from eMMC and SD card does not require a pin
> control driver to be built-in. Why is this requirement for SP platforms?
> 
> --
> With Best Regards,
> Andy Shevchenko

Because all pins of boot-device multiplex with GPIO pins.

SP7021 platforms support multi boot devices, including eMMC, SD card,
SPI-NOR flash, SPI-NAND flash. Each boot device has control-bit(s) 
to enable it.

For example #1, if control-bits of SPI-NOR flash is set 1,
GPIO 83, 84, 86, 87 are connected to SPI-NOR flash.
If control-bits of SPI-NOR flash is set 2,
GPIO 76, 78, 79, 81 are connected to SPI-NOR flash.
If control-bits of SPI-NOR flash is set 0, no pin is 
connected SPI-NOR flash.

For example #2, if control-bits of eMMC device is set 1,
GPIO 72, 73, 74, 75, 76, 77, 78, 79, 80, 81 are connected to
eMMC device.
If control-bits of eMMC device is set 0, no pin is connected 
eMMC device.

For example #3, if control-bits of SDCard device is set 1,
GPIO 65, 66, 67, 68, 69, 70 are connected to SD Card device.
If control-bits of SDCard device is set 0, no pin is connected 
SDCard device.

Note that all pins multiplex with GPIO pins.

Normally, only a boot-device is enabled. All other GPIO pins
are released for peripherals (controlled by fully-pinmux
Or group pinmux) or IO processor

Pinctrl driver is responsible for setup the pins.
If Pinctrl fails to probe, boot-device also fails to probe.


Best regards,
Wells Lu

WARNING: multiple messages have this Message-ID (diff)
From: "Wells Lu 呂芳騰" <wells.lu@sunplus.com>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Wells Lu <wellslutw@gmail.com>,
	Linus Walleij <linus.walleij@linaro.org>,
	 "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	devicetree <devicetree@vger.kernel.org>,
	linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>,
	"dvorkin@tibbo.com" <dvorkin@tibbo.com>
Subject: RE: [PATCH v5 2/2] pinctrl: Add driver for Sunplus SP7021
Date: Fri, 14 Jan 2022 10:56:10 +0000	[thread overview]
Message-ID: <b9c1876c9d0f48a3a8d7e091d47fc069@sphcmbx02.sunplus.com.tw> (raw)
In-Reply-To: <CAHp75VfxtGue7bbMm_MU2GWwWo4aZLW2Pj_U9ocCQmWr6wfGMw@mail.gmail.com>

> ...
> 
> > > > > > > > +       bool "Sunplus SP7021 PinMux and GPIO driver"
> > > > > > >
> > > > > > > Why bool and not tristate?
> > > > > >
> > > > > > Pinctrl driver is selected by many drivers in SP7021 platform.
> > > > > > We never build it as a module, but build-in to kernel.
> > > > > > So we use "bool".
> > > > > >
> > > > > > Should we set it to tristate?
> > > > >
> > > > > You still haven't answered "why", so I can't tell you.
> > > >
> > > > I am puzzled because I think I have answered "why".
> > >
> > > Nope. :-)
> > >
> > > > Because Pinctrl driver is necessary for all SP7021-based platforms.
> > >
> > > "Why?" Why is it necessary (to be built-in)?
> >
> > Pinctrl is necessary to be built-in because drivers of boot-device,
> > like eMMC, SD card, NAND flash, and NOR flash drivers, need it.
> >
> > SP7021 supports booting from eMMC, SD card, NAND flash and NOR flash
> > devices. Their drivers need Pinctrl driver probes in advance.
> 
> On x86 platforms, for example, booting from eMMC and SD card does not require a pin
> control driver to be built-in. Why is this requirement for SP platforms?
> 
> --
> With Best Regards,
> Andy Shevchenko

Because all pins of boot-device multiplex with GPIO pins.

SP7021 platforms support multi boot devices, including eMMC, SD card,
SPI-NOR flash, SPI-NAND flash. Each boot device has control-bit(s) 
to enable it.

For example #1, if control-bits of SPI-NOR flash is set 1,
GPIO 83, 84, 86, 87 are connected to SPI-NOR flash.
If control-bits of SPI-NOR flash is set 2,
GPIO 76, 78, 79, 81 are connected to SPI-NOR flash.
If control-bits of SPI-NOR flash is set 0, no pin is 
connected SPI-NOR flash.

For example #2, if control-bits of eMMC device is set 1,
GPIO 72, 73, 74, 75, 76, 77, 78, 79, 80, 81 are connected to
eMMC device.
If control-bits of eMMC device is set 0, no pin is connected 
eMMC device.

For example #3, if control-bits of SDCard device is set 1,
GPIO 65, 66, 67, 68, 69, 70 are connected to SD Card device.
If control-bits of SDCard device is set 0, no pin is connected 
SDCard device.

Note that all pins multiplex with GPIO pins.

Normally, only a boot-device is enabled. All other GPIO pins
are released for peripherals (controlled by fully-pinmux
Or group pinmux) or IO processor

Pinctrl driver is responsible for setup the pins.
If Pinctrl fails to probe, boot-device also fails to probe.


Best regards,
Wells Lu
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-01-14 10:56 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-24  7:42 [PATCH v5 0/2] This is a patch series for pinctrl driver of Sunplus SP7021 SoC Wells Lu
2021-12-24  7:42 ` Wells Lu
2021-12-24  7:42 ` [PATCH v5 1/2] dt-bindings: pinctrl: Add dt-bindings for Sunplus SP7021 Wells Lu
2021-12-24  7:42   ` Wells Lu
2021-12-25 14:48   ` Rob Herring
2021-12-25 14:48     ` Rob Herring
2021-12-26 12:44     ` Wells Lu 呂芳騰
2021-12-26 12:44       ` Wells Lu 呂芳騰
2021-12-27 16:02       ` Rob Herring
2021-12-27 16:02         ` Rob Herring
2021-12-27 16:10   ` Rob Herring
2021-12-27 16:10     ` Rob Herring
2021-12-27 17:36     ` Wells Lu 呂芳騰
2021-12-27 17:36       ` Wells Lu 呂芳騰
2021-12-24  7:42 ` [PATCH v5 2/2] pinctrl: Add driver " Wells Lu
2021-12-24  7:42   ` Wells Lu
2021-12-25 15:32   ` Andy Shevchenko
2021-12-25 15:32     ` Andy Shevchenko
2021-12-28 15:38     ` Wells Lu 呂芳騰
2021-12-28 15:38       ` Wells Lu 呂芳騰
2022-01-10 18:41       ` Andy Shevchenko
2022-01-10 18:41         ` Andy Shevchenko
2022-01-13 17:04         ` Wells Lu 呂芳騰
2022-01-13 17:04           ` Wells Lu 呂芳騰
2022-01-13 18:04           ` Andy Shevchenko
2022-01-13 18:04             ` Andy Shevchenko
2022-01-14  2:51             ` Wells Lu 呂芳騰
2022-01-14  2:51               ` Wells Lu 呂芳騰
2022-01-14  9:46               ` Andy Shevchenko
2022-01-14  9:46                 ` Andy Shevchenko
2022-01-14 10:56                 ` Wells Lu 呂芳騰 [this message]
2022-01-14 10:56                   ` Wells Lu 呂芳騰
2022-01-14 11:16                   ` Andy Shevchenko
2022-01-14 11:16                     ` Andy Shevchenko
2022-01-14 11:36                     ` Wells Lu 呂芳騰
2022-01-14 11:36                       ` Wells Lu 呂芳騰
2022-01-10 18:17     ` Wells Lu 呂芳騰
2022-01-10 18:17       ` Wells Lu 呂芳騰
2022-01-10 18:42       ` Andy Shevchenko
2022-01-10 18:42         ` Andy Shevchenko

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