* [PATCH 00/10] AYN Odin 2 support
@ 2024-04-24 15:29 Xilin Wu
2024-04-24 15:29 ` [PATCH 01/10] dt-bindings: pwm: Add SI-EN SN3112 PWM support Xilin Wu
` (9 more replies)
0 siblings, 10 replies; 11+ messages in thread
From: Xilin Wu @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm,
Xilin Wu
AYN Odin 2 is a gaming handheld based on QCS8550, which is derived
from SM8550 but without modem RF system.
This series bring support for:
* Remoteprocs
* UFS storage
* SD Card
* Type-C with USB3 10Gbps and DisplayPort (4-lane requires a pending
patch)
* PCIe0 (Wi-Fi requires the pending pwrseq series)
* Bluetooth
* Regulators
* Integrated fan with automatic speed control based on CPU temperature
* Power and volume keys
* M1, M2 buttons
* HDMI output up to 1080p 60hz
* four groups of RGB lights
* GPU
* Internal DSI display with touchscreen
Depends: [1]
[1] https://lore.kernel.org/all/20240424024508.3857602-1-quic_tengfan@quicinc.com/
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
Junhao Xie (2):
dt-bindings: pwm: Add SI-EN SN3112 PWM support
pwm: Add SI-EN SN3112 PWM support
Xilin Wu (8):
dt-bindings: display: panel: Add Synaptics TD4328
drm/panel: Add driver for Synaptics TD4328 LCD panel
arm64: dts: qcom: pmk8550: Add PWM controller
arm64: dts: qcom: sm8550: Add UART15
arm64: dts: qcom: sm8550: Update EAS properties
dt-bindings: vendor-prefixes: Add AYN Technologies
dt-bindings: arm: qcom: Add AYN Odin 2
arm64: dts: qcom: Add AYN Odin 2
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
.../bindings/display/panel/synaptics,td4328.yaml | 69 +
.../devicetree/bindings/pwm/si-en,sn3112-pwm.yaml | 55 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/pmk8550.dtsi | 10 +
arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts | 1410 ++++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8550.dtsi | 54 +-
drivers/gpu/drm/panel/Kconfig | 10 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-synaptics-td4328.c | 246 ++++
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-sn3112.c | 336 +++++
14 files changed, 2190 insertions(+), 16 deletions(-)
---
base-commit: 90388b2f9fa5f332289335f99996e252697c0242
change-id: 20240424-ayn-odin2-initial-95b7c060cd03
Best regards,
--
Xilin Wu <wuxilin123@gmail.com>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 01/10] dt-bindings: pwm: Add SI-EN SN3112 PWM support
2024-04-24 15:29 [PATCH 00/10] AYN Odin 2 support Xilin Wu
@ 2024-04-24 15:29 ` Xilin Wu
2024-04-24 15:29 ` [PATCH 02/10] " Xilin Wu
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Xilin Wu @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm,
Xilin Wu
From: Junhao Xie <bigfoot@classfun.cn>
Add a new driver for the SI-EN SN3112 12-channel 8-bit PWM LED controller.
Signed-off-by: Junhao Xie <bigfoot@classfun.cn>
---
.../devicetree/bindings/pwm/si-en,sn3112-pwm.yaml | 55 ++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/si-en,sn3112-pwm.yaml b/Documentation/devicetree/bindings/pwm/si-en,sn3112-pwm.yaml
new file mode 100644
index 000000000000..2ab229ac40ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/si-en,sn3112-pwm.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/si-en,sn3112-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SI-EN SN3112 12-channel 8-bit PWM LED controller
+
+maintainers:
+ - Junhao Xie <bigfoot@classfun.cn>
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ const: si-en,sn3112-pwm
+
+ reg:
+ const: 0x54
+ description: I2C slave address
+
+ sdb-gpios:
+ maxItems: 1
+ description: GPIO pin to hardware shutdown the device.
+
+ vdd-supply:
+ description: Chip vdd supply
+
+ "#pwm-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#pwm-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pwm@54 {
+ compatible = "si-en,sn3112-pwm";
+ reg = <0x54>;
+ sdb-gpios = <&pio 1 1 GPIO_ACTIVE_LOW>; /* PA1 */
+ vdd-supply = <®_dcdc1>;
+ #pwm-cells = <1>;
+ };
+ };
--
2.44.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 02/10] pwm: Add SI-EN SN3112 PWM support
2024-04-24 15:29 [PATCH 00/10] AYN Odin 2 support Xilin Wu
2024-04-24 15:29 ` [PATCH 01/10] dt-bindings: pwm: Add SI-EN SN3112 PWM support Xilin Wu
@ 2024-04-24 15:29 ` Xilin Wu
2024-04-24 15:29 ` [PATCH 03/10] dt-bindings: display: panel: Add Synaptics TD4328 Xilin Wu
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Xilin Wu @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm,
Xilin Wu
From: Junhao Xie <bigfoot@classfun.cn>
Add a new driver for the SI-EN SN3112 12-channel 8-bit PWM LED controller.
Signed-off-by: Junhao Xie <bigfoot@classfun.cn>
---
drivers/pwm/Kconfig | 10 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-sn3112.c | 336 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 347 insertions(+)
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 1dd7921194f5..e21c37c7991e 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -553,6 +553,16 @@ config PWM_SL28CPLD
To compile this driver as a module, choose M here: the module
will be called pwm-sl28cpld.
+config PWM_SN3112
+ tristate "SI-EN SN3112 PWM driver"
+ depends on I2C
+ select REGMAP_I2C
+ help
+ Generic PWM framework driver for SI-EN SN3112 LED controller.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-sn3112.
+
config PWM_SPEAR
tristate "STMicroelectronics SPEAr PWM support"
depends on PLAT_SPEAR || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 90913519f11a..6aab2d113159 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_PWM_RZ_MTU3) += pwm-rz-mtu3.o
obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
+obj-$(CONFIG_PWM_SN3112) += pwm-sn3112.o
obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o
obj-$(CONFIG_PWM_STI) += pwm-sti.o
diff --git a/drivers/pwm/pwm-sn3112.c b/drivers/pwm/pwm-sn3112.c
new file mode 100644
index 000000000000..38ef948602a3
--- /dev/null
+++ b/drivers/pwm/pwm-sn3112.c
@@ -0,0 +1,336 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Driver for SN3112 12-channel 8-bit PWM LED controller
+ *
+ * Copyright (c) 2024 Junhao Xie <bigfoot@classfun.cn>
+ *
+ */
+
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/regmap.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
+
+#define SN3112_CHANNELS 12
+#define SN3112_REG_ENABLE 0x00
+#define SN3112_REG_PWM_VAL 0x04
+#define SN3112_REG_PWM_EN 0x13
+#define SN3112_REG_APPLY 0x16
+#define SN3112_REG_RESET 0x17
+
+struct sn3112 {
+ struct device *pdev;
+ struct regmap *regmap;
+ struct mutex lock;
+ struct regulator *vdd;
+ uint8_t pwm_val[SN3112_CHANNELS];
+ uint8_t pwm_en_reg[3];
+ bool pwm_en[SN3112_CHANNELS];
+#if IS_ENABLED(CONFIG_GPIOLIB)
+ struct gpio_desc *sdb;
+#endif
+};
+
+static int sn3112_write_reg(struct sn3112 *priv, unsigned int reg,
+ unsigned int val)
+{
+ int err;
+
+ dev_dbg(priv->pdev, "request regmap_write 0x%x 0x%x\n", reg, val);
+ err = regmap_write(priv->regmap, reg, val);
+ if (err)
+ dev_warn_ratelimited(
+ priv->pdev,
+ "regmap_write to register 0x%x failed: %pe\n", reg,
+ ERR_PTR(err));
+
+ return err;
+}
+
+static int sn3112_set_en_reg(struct sn3112 *priv, unsigned int channel,
+ bool enabled, bool write)
+{
+ unsigned int reg, bit;
+
+ if (channel >= SN3112_CHANNELS)
+ return -EINVAL;
+
+ /* LED_EN1: BIT5:BIT3 = OUT3:OUT1 */
+ if (channel >= 0 && channel <= 2)
+ reg = 0, bit = channel + 3;
+ /* LED_EN2: BIT5:BIT0 = OUT9:OUT4 */
+ else if (channel >= 3 && channel <= 8)
+ reg = 1, bit = channel - 3;
+ /* LED_EN3: BIT2:BIT0 = OUT12:OUT10 */
+ else if (channel >= 9 && channel <= 11)
+ reg = 2, bit = channel - 9;
+ else
+ return -EINVAL;
+
+ dev_dbg(priv->pdev, "channel %u enabled %u\n", channel, enabled);
+ dev_dbg(priv->pdev, "reg %u bit %u\n", reg, bit);
+ if (enabled)
+ set_bit(bit, (ulong *)&priv->pwm_en_reg[reg]);
+ else
+ clear_bit(bit, (ulong *)&priv->pwm_en_reg[reg]);
+ dev_dbg(priv->pdev, "set enable reg %u to %u\n", reg,
+ priv->pwm_en_reg[reg]);
+
+ if (!write)
+ return 0;
+ return sn3112_write_reg(priv, SN3112_REG_PWM_EN + reg,
+ priv->pwm_en_reg[reg]);
+}
+
+static int sn3112_set_val_reg(struct sn3112 *priv, unsigned int channel,
+ uint8_t val, bool write)
+{
+ if (channel >= SN3112_CHANNELS)
+ return -EINVAL;
+ priv->pwm_val[channel] = val;
+ dev_dbg(priv->pdev, "set value reg %u to %u\n", channel,
+ priv->pwm_val[channel]);
+
+ if (!write)
+ return 0;
+ return sn3112_write_reg(priv, SN3112_REG_PWM_VAL + channel,
+ priv->pwm_val[channel]);
+}
+
+static int sn3112_write_all(struct sn3112 *priv)
+{
+ int i, ret;
+
+ /* regenerate enable register values */
+ for (i = 0; i < SN3112_CHANNELS; i++) {
+ ret = sn3112_set_en_reg(priv, i, priv->pwm_en[i], false);
+ if (ret != 0)
+ return ret;
+ }
+
+ /* use random value to clear all registers */
+ ret = sn3112_write_reg(priv, SN3112_REG_RESET, 0x66);
+ if (ret != 0)
+ return ret;
+
+ /* set software enable register */
+ ret = sn3112_write_reg(priv, SN3112_REG_ENABLE, 1);
+ if (ret != 0)
+ return ret;
+
+ /* rewrite pwm value register */
+ for (i = 0; i < SN3112_CHANNELS; i++) {
+ ret = sn3112_write_reg(priv, SN3112_REG_PWM_VAL + i,
+ priv->pwm_val[i]);
+ if (ret != 0)
+ return ret;
+ }
+
+ /* rewrite pwm enable register */
+ for (i = 0; i < 3; i++) {
+ ret = sn3112_write_reg(priv, SN3112_REG_PWM_EN + i,
+ priv->pwm_en_reg[i]);
+ if (ret != 0)
+ return ret;
+ }
+
+ /* use random value to apply changes */
+ ret = sn3112_write_reg(priv, SN3112_REG_APPLY, 0x66);
+ if (ret != 0)
+ return ret;
+
+ dev_dbg(priv->pdev, "reinitialized\n");
+ return 0;
+}
+
+static int sn3112_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct sn3112 *priv = pwmchip_get_drvdata(chip);
+
+ if (pwm->hwpwm >= SN3112_CHANNELS)
+ return -EINVAL;
+
+ dev_dbg(priv->pdev, "sn3112 request channel %u\n", pwm->hwpwm);
+ pwm->args.period = 1000000;
+ return 0;
+}
+
+static int sn3112_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ u64 val = 0;
+ struct sn3112 *priv = pwmchip_get_drvdata(chip);
+
+ if (pwm->hwpwm >= SN3112_CHANNELS)
+ return -EINVAL;
+
+ if (state->polarity != PWM_POLARITY_NORMAL)
+ return -EINVAL;
+
+ if (state->period <= 0)
+ return -EINVAL;
+
+ val = mul_u64_u64_div_u64(state->duty_cycle, 0xff, state->period);
+ dev_dbg(priv->pdev, "duty_cycle %llu period %llu\n", state->duty_cycle,
+ state->period);
+ dev_dbg(priv->pdev, "set channel %u value to %llu\n", pwm->hwpwm, val);
+ dev_dbg(priv->pdev, "set channel %u enabled to %u\n", pwm->hwpwm,
+ state->enabled);
+
+ mutex_lock(&priv->lock);
+ sn3112_set_en_reg(priv, pwm->hwpwm, state->enabled, true);
+ sn3112_set_val_reg(priv, pwm->hwpwm, val, true);
+ sn3112_write_reg(priv, SN3112_REG_APPLY, 0x66);
+ mutex_unlock(&priv->lock);
+
+ return 0;
+}
+
+static const struct pwm_ops sn3112_pwm_ops = {
+ .apply = sn3112_pwm_apply,
+ .request = sn3112_pwm_request,
+};
+
+static const struct regmap_config sn3112_regmap_i2c_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = 24,
+ .cache_type = REGCACHE_NONE,
+};
+
+static int sn3112_pwm_probe(struct i2c_client *client)
+{
+ struct pwm_chip *chip;
+ struct sn3112 *priv;
+ int ret, i;
+
+ dev_dbg(&client->dev, "probing\n");
+ chip = devm_pwmchip_alloc(&client->dev, SN3112_CHANNELS, sizeof(*priv));
+ if (IS_ERR(chip))
+ return PTR_ERR(chip);
+ priv = pwmchip_get_drvdata(chip);
+ priv->pdev = &client->dev;
+
+ /* initialize sn3112 (chip does not support read command) */
+ for (i = 0; i < SN3112_CHANNELS; i++)
+ priv->pwm_en[i] = false;
+ for (i = 0; i < SN3112_CHANNELS; i++)
+ priv->pwm_val[i] = 0;
+ for (i = 0; i < 3; i++)
+ priv->pwm_en_reg[i] = 0;
+
+ /* enable sn5112 power vdd */
+ priv->vdd = devm_regulator_get(priv->pdev, "vdd");
+ if (IS_ERR(priv->vdd)) {
+ ret = PTR_ERR(priv->vdd);
+ dev_err(priv->pdev, "Unable to get vdd regulator: %d\n", ret);
+ return ret;
+ }
+
+#if IS_ENABLED(CONFIG_GPIOLIB)
+ /* sn5112 hardware shutdown pin */
+ priv->sdb = devm_gpiod_get_optional(priv->pdev, "sdb", GPIOD_OUT_LOW);
+ if (PTR_ERR(priv->sdb) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+#endif
+
+ /* enable sn5112 power vdd */
+ ret = regulator_enable(priv->vdd);
+ if (ret < 0) {
+ dev_err(priv->pdev, "Unable to enable regulator: %d\n", ret);
+ return ret;
+ }
+
+ priv->regmap = devm_regmap_init_i2c(client, &sn3112_regmap_i2c_config);
+ if (IS_ERR(priv->regmap)) {
+ ret = PTR_ERR(priv->regmap);
+ dev_err(priv->pdev, "Failed to initialize register map: %d\n",
+ ret);
+ return ret;
+ }
+
+ i2c_set_clientdata(client, chip);
+ mutex_init(&priv->lock);
+
+ chip->ops = &sn3112_pwm_ops;
+ ret = pwmchip_add(chip);
+ if (ret < 0)
+ return ret;
+
+#if IS_ENABLED(CONFIG_GPIOLIB)
+ /* disable hardware shutdown pin */
+ if (priv->sdb)
+ gpiod_set_value(priv->sdb, 0);
+#endif
+
+ /* initialize registers */
+ ret = sn3112_write_all(priv);
+ if (ret != 0) {
+ dev_err(priv->pdev, "Failed to initialize sn3112: %d\n", ret);
+ return ret;
+ }
+
+ dev_info(&client->dev,
+ "Found SI-EN SN3112 12-channel 8-bit PWM LED controller\n");
+ return 0;
+}
+
+static void sn3112_pwm_remove(struct i2c_client *client)
+{
+ struct pwm_chip *chip = i2c_get_clientdata(client);
+ struct sn3112 *priv = pwmchip_get_drvdata(chip);
+
+ dev_dbg(priv->pdev, "remove\n");
+
+ /* set software enable register */
+ sn3112_write_reg(priv, SN3112_REG_ENABLE, 0);
+
+ /* use random value to apply changes */
+ sn3112_write_reg(priv, SN3112_REG_APPLY, 0x66);
+
+#if IS_ENABLED(CONFIG_GPIOLIB)
+ /* enable hardware shutdown pin */
+ if (priv->sdb)
+ gpiod_set_value(priv->sdb, 1);
+#endif
+
+ /* power-off sn5112 power vdd */
+ regulator_disable(priv->vdd);
+
+ pwmchip_remove(chip);
+}
+
+static const struct i2c_device_id sn3112_id[] = {
+ { "sn3112", 0 },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(i2c, sn3112_id);
+
+#ifdef CONFIG_OF
+static const struct of_device_id sn3112_dt_ids[] = {
+ { .compatible = "si-en,sn3112-pwm", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sn3112_dt_ids);
+#endif
+
+static struct i2c_driver sn3112_i2c_driver = {
+ .driver = {
+ .name = "sn3112-pwm",
+ .of_match_table = of_match_ptr(sn3112_dt_ids),
+ },
+ .probe = sn3112_pwm_probe,
+ .remove = sn3112_pwm_remove,
+ .id_table = sn3112_id,
+};
+
+module_i2c_driver(sn3112_i2c_driver);
+
+MODULE_AUTHOR("BigfootACA <bigfoot@classfun.cn>");
+MODULE_DESCRIPTION("PWM driver for SI-EN SN3112");
+MODULE_LICENSE("GPL");
--
2.44.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 03/10] dt-bindings: display: panel: Add Synaptics TD4328
2024-04-24 15:29 [PATCH 00/10] AYN Odin 2 support Xilin Wu
2024-04-24 15:29 ` [PATCH 01/10] dt-bindings: pwm: Add SI-EN SN3112 PWM support Xilin Wu
2024-04-24 15:29 ` [PATCH 02/10] " Xilin Wu
@ 2024-04-24 15:29 ` Xilin Wu
2024-04-24 15:29 ` [PATCH 04/10] drm/panel: Add driver for Synaptics TD4328 LCD panel Xilin Wu
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Xilin Wu @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm,
Xilin Wu
Synaptics TD4328 is a display driver IC used to drive LCD DSI panels.
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
.../bindings/display/panel/synaptics,td4328.yaml | 69 ++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/panel/synaptics,td4328.yaml b/Documentation/devicetree/bindings/display/panel/synaptics,td4328.yaml
new file mode 100644
index 000000000000..216f2fb22b88
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/synaptics,td4328.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/synaptics,td4328.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synaptics TD4328-based DSI display panels
+
+maintainers:
+ - Xilin Wu <wuxilin123@gmail.com>
+
+description:
+ The Synaptics TD4328 is a generic DSI Panel IC used to control
+ LCD panels.
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ contains:
+ const: syna,td4328
+
+ vdd-supply:
+ description: Digital voltage rail
+
+ vddio-supply:
+ description: Digital I/O voltage rail
+
+ reg: true
+ port: true
+
+required:
+ - compatible
+ - reg
+ - reset-gpios
+ - vdd-supply
+ - vddio-supply
+ - port
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "syna,td4328";
+ reg = <0>;
+
+ backlight = <&backlight>;
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ vdd-supply = <&vdd_lcm_2p8>;
+ vddio-supply = <&vreg_l12b_1p8>;
+
+ port {
+ panel_in_0: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+ };
+
+...
--
2.44.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 04/10] drm/panel: Add driver for Synaptics TD4328 LCD panel
2024-04-24 15:29 [PATCH 00/10] AYN Odin 2 support Xilin Wu
` (2 preceding siblings ...)
2024-04-24 15:29 ` [PATCH 03/10] dt-bindings: display: panel: Add Synaptics TD4328 Xilin Wu
@ 2024-04-24 15:29 ` Xilin Wu
2024-04-24 15:29 ` [PATCH 05/10] arm64: dts: qcom: pmk8550: Add PWM controller Xilin Wu
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Xilin Wu @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm,
Xilin Wu
Add support for the 1920x1080 LCD panel driven by the Synaptics
TD4328 IC, as found on AYN Odin 2.
Co-developed-by: Junhao Xie <bigfoot@classfun.cn>
Signed-off-by: Junhao Xie <bigfoot@classfun.cn>
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
drivers/gpu/drm/panel/Kconfig | 10 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-synaptics-td4328.c | 246 +++++++++++++++++++++++++
3 files changed, 257 insertions(+)
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index ab67789e59a2..69852a35eccd 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -845,6 +845,16 @@ config DRM_PANEL_SYNAPTICS_R63353
Say Y if you want to enable support for panels based on the
Synaptics R63353 controller.
+config DRM_PANEL_SYNAPTICS_TD4328
+ tristate "Synaptics TD4328-based panels"
+ depends on OF
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ select DRM_KMS_HELPER
+ help
+ Say Y if you want to enable support for panels based on the
+ Synaptics TD4328 controller.
+
config DRM_PANEL_TDO_TL070WSH30
tristate "TDO TL070WSH30 DSI panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 0b40b010e8e7..927013e3eb11 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -81,6 +81,7 @@ obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701) += panel-sitronix-st7701.o
obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7703) += panel-sitronix-st7703.o
obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o
obj-$(CONFIG_DRM_PANEL_SYNAPTICS_R63353) += panel-synaptics-r63353.o
+obj-$(CONFIG_DRM_PANEL_SYNAPTICS_TD4328) += panel-synaptics-td4328.o
obj-$(CONFIG_DRM_PANEL_SONY_ACX565AKM) += panel-sony-acx565akm.o
obj-$(CONFIG_DRM_PANEL_SONY_TD4353_JDI) += panel-sony-td4353-jdi.o
obj-$(CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521) += panel-sony-tulip-truly-nt35521.o
diff --git a/drivers/gpu/drm/panel/panel-synaptics-td4328.c b/drivers/gpu/drm/panel/panel-synaptics-td4328.c
new file mode 100644
index 000000000000..0fb0ddd9373d
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-synaptics-td4328.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree.
+ * Copyright (c) 2024 Xilin Wu <wuxilin123@gmail.com>
+ * Copyright (c) 2024 Junhao Xie <bigfoot@classfun.cn>
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/regulator/consumer.h>
+
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_probe_helper.h>
+
+struct td4328 {
+ struct drm_panel panel;
+ struct mipi_dsi_device *dsi;
+ struct regulator_bulk_data supplies[2];
+ struct gpio_desc *reset_gpio;
+};
+
+static inline struct td4328 *to_td4328(struct drm_panel *panel)
+{
+ return container_of(panel, struct td4328, panel);
+}
+
+static void td4328_reset(struct td4328 *ctx)
+{
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ usleep_range(10000, 11000);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ usleep_range(10000, 11000);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ usleep_range(10000, 11000);
+}
+
+static int td4328_on(struct td4328 *ctx)
+{
+ struct mipi_dsi_device *dsi = ctx->dsi;
+ struct device *dev = &dsi->dev;
+ int ret;
+
+ dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+
+ mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00);
+ mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x31);
+ mipi_dsi_dcs_write_seq(dsi, 0xd6, 0x00);
+
+ ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+ if (ret < 0) {
+ dev_err(dev, "Failed to exit sleep mode: %d\n", ret);
+ return ret;
+ }
+ msleep(70);
+
+ ret = mipi_dsi_dcs_set_display_on(dsi);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set display on: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int td4328_off(struct td4328 *ctx)
+{
+ struct mipi_dsi_device *dsi = ctx->dsi;
+ struct device *dev = &dsi->dev;
+ int ret;
+
+ dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
+
+ ret = mipi_dsi_dcs_set_display_off(dsi);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set display off: %d\n", ret);
+ return ret;
+ }
+ msleep(50);
+
+ ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enter sleep mode: %d\n", ret);
+ return ret;
+ }
+ msleep(120);
+
+ return 0;
+}
+
+static int td4328_prepare(struct drm_panel *panel)
+{
+ struct td4328 *ctx = to_td4328(panel);
+ struct device *dev = &ctx->dsi->dev;
+ int ret;
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable regulators: %d\n", ret);
+ return ret;
+ }
+
+ td4328_reset(ctx);
+
+ ret = td4328_on(ctx);
+ if (ret < 0) {
+ dev_err(dev, "Failed to initialize panel: %d\n", ret);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int td4328_unprepare(struct drm_panel *panel)
+{
+ struct td4328 *ctx = to_td4328(panel);
+ struct device *dev = &ctx->dsi->dev;
+ int ret;
+
+ ret = td4328_off(ctx);
+ if (ret < 0)
+ dev_err(dev, "Failed to un-initialize panel: %d\n", ret);
+
+ regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
+
+ return 0;
+}
+
+static const struct drm_display_mode td4328_mode = {
+ .clock = (1080 + 93 + 1 + 47) * (1920 + 40 + 2 + 60) * 60 / 1000,
+ .hdisplay = 1080,
+ .hsync_start = 1080 + 93,
+ .hsync_end = 1080 + 93 + 1,
+ .htotal = 1080 + 93 + 1 + 47,
+ .vdisplay = 1920,
+ .vsync_start = 1920 + 40,
+ .vsync_end = 1920 + 40 + 2,
+ .vtotal = 1920 + 40 + 2 + 60,
+ .width_mm = 75,
+ .height_mm = 133,
+ .type = DRM_MODE_TYPE_DRIVER,
+};
+
+static int td4328_get_modes(struct drm_panel *panel,
+ struct drm_connector *connector)
+{
+ return drm_connector_helper_get_modes_fixed(connector, &td4328_mode);
+}
+
+static enum drm_panel_orientation td4328_get_orientation(struct drm_panel *panel)
+{
+ return DRM_MODE_PANEL_ORIENTATION_RIGHT_UP;
+}
+
+static const struct drm_panel_funcs td4328_panel_funcs = {
+ .prepare = td4328_prepare,
+ .disable = td4328_unprepare,
+ .get_modes = td4328_get_modes,
+ .get_orientation = td4328_get_orientation,
+};
+
+static int td4328_probe(struct mipi_dsi_device *dsi)
+{
+ struct device *dev = &dsi->dev;
+ struct td4328 *ctx;
+ int ret;
+
+ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+
+ ctx->supplies[0].supply = "vddio";
+ ctx->supplies[1].supply = "vdd";
+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
+ ctx->supplies);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to get regulators\n");
+
+ ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+ if (IS_ERR(ctx->reset_gpio))
+ return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio),
+ "Failed to get reset-gpios\n");
+
+ ctx->dsi = dsi;
+ mipi_dsi_set_drvdata(dsi, ctx);
+
+ dsi->lanes = 4;
+ dsi->format = MIPI_DSI_FMT_RGB888;
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+ MIPI_DSI_CLOCK_NON_CONTINUOUS;
+
+ drm_panel_init(&ctx->panel, dev, &td4328_panel_funcs,
+ DRM_MODE_CONNECTOR_DSI);
+ ctx->panel.prepare_prev_first = true;
+
+ ret = drm_panel_of_backlight(&ctx->panel);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to get backlight\n");
+
+ drm_panel_add(&ctx->panel);
+
+ ret = mipi_dsi_attach(dsi);
+ if (ret < 0) {
+ dev_err_probe(dev, ret, "Failed to attach to DSI host\n");
+ drm_panel_remove(&ctx->panel);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void td4328_remove(struct mipi_dsi_device *dsi)
+{
+ struct td4328 *ctx = mipi_dsi_get_drvdata(dsi);
+ int ret;
+
+ ret = mipi_dsi_detach(dsi);
+ if (ret < 0)
+ dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
+
+ drm_panel_remove(&ctx->panel);
+}
+
+static const struct of_device_id td4328_of_match[] = {
+ { .compatible = "syna,td4328" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, td4328_of_match);
+
+static struct mipi_dsi_driver td4328_driver = {
+ .probe = td4328_probe,
+ .remove = td4328_remove,
+ .driver = {
+ .name = "panel-td4328",
+ .of_match_table = td4328_of_match,
+ },
+};
+module_mipi_dsi_driver(td4328_driver);
+
+MODULE_DESCRIPTION("DRM driver for td4328-equipped DSI panels");
+MODULE_LICENSE("GPL");
--
2.44.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 05/10] arm64: dts: qcom: pmk8550: Add PWM controller
2024-04-24 15:29 [PATCH 00/10] AYN Odin 2 support Xilin Wu
` (3 preceding siblings ...)
2024-04-24 15:29 ` [PATCH 04/10] drm/panel: Add driver for Synaptics TD4328 LCD panel Xilin Wu
@ 2024-04-24 15:29 ` Xilin Wu
2024-04-24 15:29 ` [PATCH 06/10] arm64: dts: qcom: sm8550: Add UART15 Xilin Wu
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Xilin Wu @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm,
Xilin Wu
Add the PWM function to the pmk8550 dtsi, which is usually used
to control PWM backlight on platforms using this PMIC.
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
arch/arm64/boot/dts/qcom/pmk8550.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qcom/pmk8550.dtsi
index c7ac9b2eaacf..8d43fbb85263 100644
--- a/arch/arm64/boot/dts/qcom/pmk8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi
@@ -73,5 +73,15 @@ pmk8550_gpios: gpio@8800 {
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ pmk8550_pwm: pwm {
+ compatible = "qcom,pmk8550-pwm";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pwm-cells = <2>;
+
+ status = "disabled";
+ };
};
};
--
2.44.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 06/10] arm64: dts: qcom: sm8550: Add UART15
2024-04-24 15:29 [PATCH 00/10] AYN Odin 2 support Xilin Wu
` (4 preceding siblings ...)
2024-04-24 15:29 ` [PATCH 05/10] arm64: dts: qcom: pmk8550: Add PWM controller Xilin Wu
@ 2024-04-24 15:29 ` Xilin Wu
2024-04-24 15:29 ` [PATCH 07/10] arm64: dts: qcom: sm8550: Update EAS properties Xilin Wu
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Xilin Wu @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm,
Xilin Wu
Add uart15 node for UART bus present on sm8550 SoC.
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index bc5aeb05ffc3..b8bbe88e770f 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1122,6 +1122,20 @@ spi15: spi@89c000 {
#size-cells = <0>;
status = "disabled";
};
+
+ uart15: serial@89c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x89c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart15_default>;
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
};
i2c_master_hub_0: geniqup@9c0000 {
@@ -3856,6 +3870,14 @@ qup_uart14_cts_rts: qup-uart14-cts-rts-state {
bias-pull-down;
};
+ qup_uart15_default: qup-uart15-default-state {
+ /* TX, RX */
+ pins = "gpio74", "gpio75";
+ function = "qup2_se7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
sdc2_sleep: sdc2-sleep-state {
clk-pins {
pins = "sdc2_clk";
--
2.44.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 07/10] arm64: dts: qcom: sm8550: Update EAS properties
2024-04-24 15:29 [PATCH 00/10] AYN Odin 2 support Xilin Wu
` (5 preceding siblings ...)
2024-04-24 15:29 ` [PATCH 06/10] arm64: dts: qcom: sm8550: Add UART15 Xilin Wu
@ 2024-04-24 15:29 ` Xilin Wu
2024-04-24 15:29 ` [PATCH 08/10] dt-bindings: vendor-prefixes: Add AYN Technologies Xilin Wu
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Xilin Wu @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm,
Xilin Wu
The original values provided by Qualcomm appear to be quite
inaccurate. Specifically, some heavy gaming tasks could be
improperly assigned to the A510 cores by the scheduler, resulting
in a CPU bottleneck. This update to the EAS properties aims to
enhance the user experience across various scenarios.
The power numbers were obtained using a Type-C power meter, which
was directly connected to the battery connector on the AYN Odin 2
motherboard, acting as a fake battery.
It should be noted that the A715 cores seem less efficient than the
A710 cores. Therefore, an average value has been assigned to them,
considering that the A715 and A710 cores share a single cpufreq
domain.
Cortex-A510 cores:
441 kHz, 564 mV, 43 mW, 350 Cx
556 kHz, 580 mV, 59 mW, 346 Cx
672 kHz, 592 mV, 71 mW, 312 Cx
787 kHz, 604 mV, 83 mW, 290 Cx
902 kHz, 608 mV, 96 mW, 288 Cx
1017 kHz, 624 mV, 107 mW, 264 Cx
1113 kHz, 636 mV, 117 mW, 252 Cx
1228 kHz, 652 mV, 130 mW, 240 Cx
1344 kHz, 668 mV, 146 mW, 235 Cx
1459 kHz, 688 mV, 155 mW, 214 Cx
1555 kHz, 704 mV, 166 mW, 205 Cx
1670 kHz, 724 mV, 178 mW, 192 Cx
1785 kHz, 744 mV, 197 mW, 189 Cx
1900 kHz, 764 mV, 221 mW, 190 Cx
2016 kHz, 784 mV, 243 mW, 188 Cx
Your dynamic-power-coefficient for cpu 1: 251
Cortex-A715 cores:
614 kHz, 572 mV, 97 mW, 470 Cx
729 kHz, 592 mV, 123 mW, 473 Cx
844 kHz, 608 mV, 152 mW, 486 Cx
940 kHz, 624 mV, 178 mW, 485 Cx
1056 kHz, 644 mV, 207 mW, 465 Cx
1171 kHz, 656 mV, 243 mW, 480 Cx
1286 kHz, 672 mV, 271 mW, 459 Cx
1401 kHz, 692 mV, 310 mW, 454 Cx
1536 kHz, 716 mV, 368 mW, 462 Cx
1651 kHz, 740 mV, 416 mW, 454 Cx
1785 kHz, 760 mV, 492 mW, 475 Cx
1920 kHz, 784 mV, 544 mW, 457 Cx
2054 kHz, 804 mV, 613 mW, 458 Cx
2188 kHz, 828 mV, 702 mW, 465 Cx
2323 kHz, 852 mV, 782 mW, 461 Cx
2457 kHz, 876 mV, 895 mW, 473 Cx
2592 kHz, 896 mV, 1020 mW, 490 Cx
2707 kHz, 920 mV, 1140 mW, 498 Cx
2803 kHz, 940 mV, 1215 mW, 490 Cx
Your dynamic-power-coefficient for cpu 3: 472
Cortex-A710 cores:
614 kHz, 572 mV, 91 mW, 388 Cx
729 kHz, 592 mV, 116 mW, 424 Cx
844 kHz, 608 mV, 143 mW, 443 Cx
940 kHz, 624 mV, 165 mW, 434 Cx
1056 kHz, 644 mV, 195 mW, 430 Cx
1171 kHz, 656 mV, 218 mW, 414 Cx
1286 kHz, 672 mV, 250 mW, 415 Cx
1401 kHz, 692 mV, 286 mW, 412 Cx
1536 kHz, 716 mV, 331 mW, 407 Cx
1651 kHz, 740 mV, 374 mW, 401 Cx
1785 kHz, 760 mV, 439 mW, 417 Cx
1920 kHz, 784 mV, 495 mW, 411 Cx
2054 kHz, 804 mV, 557 mW, 412 Cx
2188 kHz, 828 mV, 632 mW, 415 Cx
2323 kHz, 852 mV, 721 mW, 422 Cx
2457 kHz, 876 mV, 813 mW, 427 Cx
2592 kHz, 896 mV, 912 mW, 435 Cx
2707 kHz, 920 mV, 1019 mW, 442 Cx
2803 kHz, 940 mV, 1087 mW, 436 Cx
Your dynamic-power-coefficient for cpu 5: 421
Cortex-X3 core:
729 kHz, 568 mV, 252 mW, 1110 Cx
864 kHz, 580 mV, 312 mW, 1097 Cx
998 kHz, 592 mV, 379 mW, 1109 Cx
1132 kHz, 608 mV, 453 mW, 1099 Cx
1248 kHz, 624 mV, 517 mW, 1067 Cx
1363 kHz, 636 mV, 587 mW, 1067 Cx
1478 kHz, 648 mV, 657 mW, 1058 Cx
1593 kHz, 664 mV, 739 mW, 1049 Cx
1708 kHz, 680 mV, 813 mW, 1020 Cx
1843 kHz, 704 mV, 940 mW, 1021 Cx
1977 kHz, 724 mV, 1054 mW, 1007 Cx
2092 kHz, 740 mV, 1201 mW, 1045 Cx
2227 kHz, 768 mV, 1358 mW, 1029 Cx
2342 kHz, 788 mV, 1486 mW, 1016 Cx
2476 kHz, 812 mV, 1711 mW, 1046 Cx
2592 kHz, 836 mV, 1846 mW, 1014 Cx
2726 kHz, 856 mV, 2046 mW, 1020 Cx
2841 kHz, 880 mV, 2266 mW, 1027 Cx
2956 kHz, 908 mV, 2616 mW, 1074 Cx
3187 kHz, 956 mV, 3326 mW, 1147 Cx
Your dynamic-power-coefficient for cpu 7: 1057
7-zip benchmark single-core MIPS:
2128 4416 4632 6686
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index b8bbe88e770f..a84dd7f6ebc1 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -79,8 +79,8 @@ CPU0: cpu@0 {
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <326>;
+ dynamic-power-coefficient = <251>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
@@ -105,8 +105,8 @@ CPU1: cpu@100 {
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <326>;
+ dynamic-power-coefficient = <251>;
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
@@ -126,8 +126,8 @@ CPU2: cpu@200 {
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <326>;
+ dynamic-power-coefficient = <251>;
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
@@ -147,8 +147,8 @@ CPU3: cpu@300 {
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- capacity-dmips-mhz = <1792>;
- dynamic-power-coefficient = <270>;
+ capacity-dmips-mhz = <693>;
+ dynamic-power-coefficient = <447>;
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
@@ -168,8 +168,8 @@ CPU4: cpu@400 {
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- capacity-dmips-mhz = <1792>;
- dynamic-power-coefficient = <270>;
+ capacity-dmips-mhz = <693>;
+ dynamic-power-coefficient = <447>;
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
@@ -189,8 +189,8 @@ CPU5: cpu@500 {
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- capacity-dmips-mhz = <1792>;
- dynamic-power-coefficient = <270>;
+ capacity-dmips-mhz = <693>;
+ dynamic-power-coefficient = <447>;
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
@@ -210,8 +210,8 @@ CPU6: cpu@600 {
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- capacity-dmips-mhz = <1792>;
- dynamic-power-coefficient = <270>;
+ capacity-dmips-mhz = <693>;
+ dynamic-power-coefficient = <447>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
@@ -231,8 +231,8 @@ CPU7: cpu@700 {
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 2>;
- capacity-dmips-mhz = <1894>;
- dynamic-power-coefficient = <588>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <1057>;
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
--
2.44.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 08/10] dt-bindings: vendor-prefixes: Add AYN Technologies
2024-04-24 15:29 [PATCH 00/10] AYN Odin 2 support Xilin Wu
` (6 preceding siblings ...)
2024-04-24 15:29 ` [PATCH 07/10] arm64: dts: qcom: sm8550: Update EAS properties Xilin Wu
@ 2024-04-24 15:29 ` Xilin Wu
2024-04-24 15:29 ` [PATCH 09/10] dt-bindings: arm: qcom: Add AYN Odin 2 Xilin Wu
2024-04-24 15:29 ` [PATCH 10/10] arm64: dts: " Xilin Wu
9 siblings, 0 replies; 11+ messages in thread
From: Xilin Wu @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm,
Xilin Wu
Add an entry for AYN Technologies (https://www.ayntec.com/)
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index e4aeeb5fe4d1..c2365b0f4184 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -194,6 +194,8 @@ patternProperties:
description: Axentia Technologies AB
"^axis,.*":
description: Axis Communications AB
+ "^ayn,.*":
+ description: AYN Technologies Co., Ltd.
"^azoteq,.*":
description: Azoteq (Pty) Ltd
"^azw,.*":
--
2.44.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 09/10] dt-bindings: arm: qcom: Add AYN Odin 2
2024-04-24 15:29 [PATCH 00/10] AYN Odin 2 support Xilin Wu
` (7 preceding siblings ...)
2024-04-24 15:29 ` [PATCH 08/10] dt-bindings: vendor-prefixes: Add AYN Technologies Xilin Wu
@ 2024-04-24 15:29 ` Xilin Wu
2024-04-24 15:29 ` [PATCH 10/10] arm64: dts: " Xilin Wu
9 siblings, 0 replies; 11+ messages in thread
From: Xilin Wu @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm,
Xilin Wu
This documents AYN Odin 2 which is a gaming handheld by AYN based on
the QCS8550 SoC.
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 090fc5fda9b0..8e991f2bd9d8 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -1003,6 +1003,7 @@ properties:
- items:
- enum:
+ - ayn,odin2
- qcom,qcs8550-aim300-aiot
- const: qcom,qcs8550-aim300
- const: qcom,qcs8550
--
2.44.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 10/10] arm64: dts: qcom: Add AYN Odin 2
2024-04-24 15:29 [PATCH 00/10] AYN Odin 2 support Xilin Wu
` (8 preceding siblings ...)
2024-04-24 15:29 ` [PATCH 09/10] dt-bindings: arm: qcom: Add AYN Odin 2 Xilin Wu
@ 2024-04-24 15:29 ` Xilin Wu
9 siblings, 0 replies; 11+ messages in thread
From: Xilin Wu @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm,
Xilin Wu
AYN Odin 2 is a gaming handheld based on QCS8550, which is derived
from SM8550 but without modem RF system.
This commit brings support for:
* Remoteprocs
* UFS storage
* SD Card
* Type-C with USB3 10Gbps and DisplayPort (4-lane requires a pending
patch)
* PCIe0 (Wi-Fi requires the pending pwrseq series)
* Bluetooth
* Regulators
* Integrated fan with automatic speed control based on CPU temperature
* Power and volume keys
* M1, M2 buttons
* HDMI output up to 1080p 60hz
* four groups of RGB lights
* GPU
* Internal DSI display with touchscreen
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts | 1410 ++++++++++++++++++++++++
2 files changed, 1411 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index c46c10d85697..070c0d996059 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -97,6 +97,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs8550-ayn-odin2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts b/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts
new file mode 100644
index 000000000000..bfe353d3c53e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts
@@ -0,0 +1,1410 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Xilin Wu <wuxilin123@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/arm/qcom,ids.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "qcs8550.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 5
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+
+/*
+ * The SoC being used on this product doesn't feature modem
+ * and camera subsystem.
+ * Variant: 202-AB
+ * FEATURE_ID: 0x8
+ */
+
+/delete-node/ &mpss_mem;
+/delete-node/ &q6_mpss_dtb_mem;
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &ipa_gsi_mem;
+/delete-node/ &camera_mem;
+/delete-node/ &mpss_dsm_mem;
+/delete-node/ &camcc;
+/delete-node/ &remoteproc_mpss;
+
+/ {
+ model = "AYN Odin 2";
+ compatible = "ayn,odin2", "qcom,qcs8550", "qcom,sm8550";
+ chassis-type = "handset";
+
+ qcom,msm-id = <QCOM_ID_QCS8550 0x20000>;
+ qcom,board-id = <0x1001f 0>;
+
+ aliases {
+ serial0 = &uart7;
+ serial1 = &uart14;
+ serial2 = &uart15;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pmk8550_pwm 0 860000>;
+ brightness-levels = <1023 0>;
+ num-interpolated-steps = <1023>;
+ default-brightness-level = <600>;
+ power-supply = <&vph_pwr>;
+ enable-gpios = <&pmk8550_gpios 5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_backlight_default>;
+ status = "okay";
+ };
+
+ fan_pwr: fan-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "fan_pwr";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&tlmm 109 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&fan_pwr_en>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>, <&m1_m2_keys_default>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+
+ m1-button {
+ label = "M1";
+ linux,code = <BTN_TRIGGER_HAPPY1>;
+ gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+ };
+
+ m2-button {
+ label = "M2";
+ linux,code = <BTN_TRIGGER_HAPPY2>;
+ gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "d";
+ hpd-gpios = <&tlmm 9 GPIO_ACTIVE_HIGH>;
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<8912_out>;
+ };
+ };
+ };
+
+ hdmi_pwr: hdmi-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "hdmi_pwr";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 10 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_lcm_2p8: vdd-lcm-2p8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_lcm_2p8";
+
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ gpio = <&tlmm 142 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ led_left_side: led-controller-1 {
+ compatible = "pwm-leds-multicolor";
+
+ multi-led {
+ label = "left-side";
+ color = <LED_COLOR_ID_RGB>;
+ max-brightness = <255>;
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ pwms = <&pwm_rgb_left 0>;
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm_rgb_left 1>;
+ };
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ pwms = <&pwm_rgb_left 2>;
+ };
+ };
+ };
+
+ led_left_joystick: led-controller-2 {
+ compatible = "pwm-leds-multicolor";
+
+ multi-led {
+ label = "left-joystick";
+ color = <LED_COLOR_ID_RGB>;
+ max-brightness = <255>;
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ pwms = <&pwm_rgb_left 6>;
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm_rgb_left 7>;
+ };
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ pwms = <&pwm_rgb_left 8>;
+ };
+ };
+ };
+
+ led_right_side: led-controller-3 {
+ compatible = "pwm-leds-multicolor";
+
+ multi-led {
+ label = "right-side";
+ color = <LED_COLOR_ID_RGB>;
+ max-brightness = <255>;
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ pwms = <&pwm_rgb_right 0>;
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm_rgb_right 1>;
+ };
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ pwms = <&pwm_rgb_right 2>;
+ };
+ };
+ };
+
+ led_right_joystick: led-controller-4 {
+ compatible = "pwm-leds-multicolor";
+
+ multi-led {
+ label = "right-joystick";
+ color = <LED_COLOR_ID_RGB>;
+ max-brightness = <255>;
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ pwms = <&pwm_rgb_right 6>;
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm_rgb_right 7>;
+ };
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ pwms = <&pwm_rgb_right 8>;
+ };
+ };
+ };
+
+ mcu_3v3: mcu-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "mcu_3v3";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&usb0_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 40 65 75 90 100 120 150>;
+ #cooling-cells = <2>;
+ fan-supply = <&fan_pwr>;
+ pwms = <&pm8550_pwm 3 100000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_out_default &fan_int>;
+
+ pulses-per-revolution = <4>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ thermal-zones {
+ cpuss0-thermal {
+ trips {
+ cpuss0_active0: trip-point2 {
+ temperature = <50000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active1: trip-point3 {
+ temperature = <55000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active2: trip-point4 {
+ temperature = <60000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active3: trip-point5 {
+ temperature = <65000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active4: trip-point6 {
+ temperature = <70000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active5: trip-point7 {
+ temperature = <75000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active6: trip-point8 {
+ temperature = <80000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpuss0_active0>;
+ cooling-device = <&fan 0 1>;
+ };
+ map1 {
+ trip = <&cpuss0_active1>;
+ cooling-device = <&fan 1 2>;
+ };
+ map2 {
+ trip = <&cpuss0_active2>;
+ cooling-device = <&fan 2 3>;
+ };
+ map3 {
+ trip = <&cpuss0_active3>;
+ cooling-device = <&fan 3 4>;
+ };
+ map4 {
+ trip = <&cpuss0_active4>;
+ cooling-device = <&fan 4 5>;
+ };
+ map5 {
+ trip = <&cpuss0_active5>;
+ cooling-device = <&fan 5 6>;
+ };
+ map6 {
+ trip = <&cpuss0_active6>;
+ cooling-device = <&fan 6 7>;
+ };
+ };
+ };
+ };
+
+ usb0-sbu-mux {
+ compatible = "pericom,pi3usb102", "gpio-sbu-mux";
+
+ enable-gpios = <&tlmm 140 GPIO_ACTIVE_LOW>;
+ select-gpios = <&tlmm 141 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_sbu_default>;
+
+ mode-switch;
+ orientation-switch;
+
+ port {
+ usb0_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l11-supply = <&vreg_s4g_1p25>;
+ vdd-l12-supply = <&vreg_s6g_1p86>;
+ vdd-l15-supply = <&vreg_s6g_1p86>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b_1p8: ldo10 {
+ regulator-name = "vreg_l10b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* Setting regulator-allow-set-load here will crash the device */
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_l1c_1p2: ldo1 {
+ regulator-name = "vreg_l1c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_0p9: ldo3 {
+ regulator-name = "vreg_l3c_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* ldo2 supplies SM8550 VDD_LPI_MX */
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vreg_s4e_0p95: smps4 {
+ regulator-name = "vreg_s4e_0p95";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <984000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5e_1p08: smps5 {
+ regulator-name = "vreg_s5e_1p08";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1e_0p88: ldo1 {
+ regulator-name = "vreg_l1e_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2e_0p9: ldo2 {
+ regulator-name = "vreg_l2e_0p9";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ vreg_s4f_0p5: smps4 {
+ regulator-name = "vreg_s4f_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_0p9: ldo1 {
+ regulator-name = "vreg_l1f_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_0p88: ldo2 {
+ regulator-name = "vreg_l2f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_0p88: ldo3 {
+ regulator-name = "vreg_l3f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "g";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vreg_s1g_1p25: smps1 {
+ regulator-name = "vreg_s1g_1p25";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2g_0p85: smps2 {
+ regulator-name = "vreg_s2g_0p85";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1036000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_0p8: smps3 {
+ regulator-name = "vreg_s3g_0p8";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_1p25: smps4 {
+ regulator-name = "vreg_s4g_1p25";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
+ };
+
+ vreg_s5g_0p85: smps5 {
+ regulator-name = "vreg_s5g_0p85";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6g_1p86: smps6 {
+ regulator-name = "vreg_s6g_1p86";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1144000>;
+ regulator-max-microvolt = <1256000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2g_1p1: ldo2 {
+ regulator-name = "vreg_l2g_1p1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpi_dma2 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ firmware-name = "qcom/sm8550/ayn/odin2/a740_zap.mbn";
+ };
+};
+
+&hub_i2c0_data_clk {
+ /delete-property/ bias-pull-up;
+ bias-disable;
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ pwm_rgb_left: pwm@54 {
+ compatible = "si-en,sn3112-pwm";
+ reg = <0x54>;
+ sdb-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&mcu_3v3>;
+ #pwm-cells = <1>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchscreen@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts-extended = <&tlmm 25 0x2008>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&ts_int_default>;
+ pinctrl-1 = <&ts_int_sleep>;
+
+ vio-supply = <&vreg_l12b_1p8>;
+
+ syna,startup-delay-ms = <200>;
+ syna,reset-delay-ms = <200>;
+
+ rmi4-f01@1 {
+ syna,nosleep-mode = <0x1>;
+ reg = <0x1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ syna,rezero-wait-ms = <20>;
+ syna,clip-x-low = <0>;
+ syna,clip-y-low = <0>;
+ syna,clip-x-high = <1080>;
+ syna,clip-y-high = <1920>;
+ syna,sensor-type = <1>;
+ touchscreen-inverted-x;
+ };
+ };
+};
+
+&i2c12 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ pwm_rgb_right: pwm@54 {
+ compatible = "si-en,sn3112-pwm";
+ reg = <0x54>;
+ sdb-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&mcu_3v3>;
+ #pwm-cells = <1>;
+ };
+};
+
+&i2c_master_hub_0 {
+ status = "okay";
+};
+
+&i2c_hub_0 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ hdmi-bridge@48 {
+ compatible = "lontium,lt8912b";
+ reg = <0x48> ;
+ reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>;
+
+ vdd-supply = <&hdmi_pwr>;
+ vccmipirx-supply = <&hdmi_pwr>;
+ vccsysclk-supply = <&hdmi_pwr>;
+ vcclvdstx-supply = <&hdmi_pwr>;
+ vcchdmitx-supply = <&hdmi_pwr>;
+ vcclvdspll-supply = <&hdmi_pwr>;
+ vcchdmipll-supply = <&hdmi_pwr>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_out_in: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lt8912_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&i2c_hub_2 {
+ status = "okay";
+
+ /* Awinic AW88166 audio amplifier @ 34, 35 */
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp0 {
+ status = "okay";
+};
+
+&mdss_dp0_out {
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&hdmi_out_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+ status = "okay";
+};
+
+&mdss_dsi1 {
+ vdda-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+
+ panel: panel@0 {
+ compatible = "syna,td4328";
+ reg = <0>;
+
+ pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>;
+ pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>;
+ pinctrl-names = "default", "sleep";
+
+ vdd-supply = <&vdd_lcm_2p8>;
+ vddio-supply = <&vreg_l12b_1p8>;
+
+ backlight = <&backlight>;
+ /* touchscreen and display panel share the same reset gpio! */
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&mdss_dsi1_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi1_out {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi1_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+ status = "okay";
+};
+
+&pcie0 {
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ max-link-speed = <2>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pm8550_gpios {
+ pwm_out_default: pwm-out-default-state {
+ pins = "gpio8";
+ function = "func1";
+ input-disable;
+ output-enable;
+ output-low;
+ bias-disable;
+ power-source = <1>;
+ };
+
+ sdc2_card_det_n: sdc2-card-det-state {
+ pins = "gpio12";
+ function = "normal";
+ input-enable;
+ output-disable;
+ bias-pull-up;
+ power-source = <1>; /* 1.8 V */
+ };
+
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pm8550_pwm {
+ status = "okay";
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_CHARGING;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+};
+
+&pm8550b_eusb2_repeater {
+ qcom,tune-usb2-disc-thres = /bits/ 8 <0x6>;
+ qcom,tune-usb2-amplitude = /bits/ 8 <0xb>;
+ qcom,tune-usb2-preem = /bits/ 8 <0x3>;
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&pmk8550_gpios {
+ pwm_backlight_default: pwm-backlight-default-state {
+ pins = "gpio5";
+ function = "func3";
+ input-disable;
+ output-enable;
+ output-low;
+ bias-disable;
+ power-source = <0>;
+ qcom,drive-strength = <2>;
+ };
+};
+
+&pmk8550_pwm {
+ status = "okay";
+};
+
+&pmk8550_rtc {
+ nvmem-cells = <&rtc_offset>;
+ nvmem-cell-names = "offset";
+
+ status = "okay";
+};
+
+&pmk8550_sdam_2 {
+ status = "okay";
+
+ rtc_offset: rtc-offset@bc {
+ reg = <0xbc 0x4>;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8550/ayn/odin2/adsp.mbn",
+ "qcom/sm8550/ayn/odin2/adsp_dtb.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm8550/ayn/odin2/cdsp.mbn",
+ "qcom/sm8550/ayn/odin2/cdsp_dtb.mbn";
+ status = "okay";
+};
+
+&sdhc_2 {
+ cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+
+ /* SDR104 does seem to be working on this device*/
+ /delete-property/ sdhci-caps-mask;
+ qcom,dll-config = <0x0007442c>;
+
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&tlmm {
+ gpio-reserved-ranges = <32 8>;
+
+ fan_int: fan-int-state {
+ pins = "gpio13";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ fan_pwr_en: fan-pwr-en-state {
+ pins = "gpio109";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+
+ m1_m2_keys_default: m1-m2-keys-default-state {
+ pins = "gpio57", "gpio58";
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ ts_int_default: ts-int-default-state {
+ pins = "gpio25";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ ts_int_sleep: ts-int-sleep-state {
+ pins = "gpio25";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ bt_default: bt-default-state {
+ bt-en-pins {
+ pins = "gpio81";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ sw-ctrl-pins {
+ pins = "gpio82";
+ function = "gpio";
+ bias-pull-down;
+ };
+ };
+
+ usb0_sbu_default: usb0-sbu-state {
+ oe-n-pins {
+ pins = "gpio140";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <16>;
+ output-high;
+ };
+
+ sel-pins {
+ pins = "gpio141";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <16>;
+ };
+ };
+
+ sde_dsi_active: sde-dsi-active-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ sde_dsi_suspend: sde-dsi-suspend-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ sde_te_active: sde-te-active-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ sde_te_suspend: sde-te-suspend-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&uart14 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn7850-bt";
+
+ vddio-supply = <&vreg_l15b_1p8>;
+ vddaon-supply = <&vreg_s4e_0p95>;
+ vdddig-supply = <&vreg_s4e_0p95>;
+ vddrfa0p8-supply = <&vreg_s4e_0p95>;
+ vddrfa1p2-supply = <&vreg_s4g_1p25>;
+ vddrfa1p9-supply = <&vreg_s6g_1p86>;
+
+ max-speed = <3200000>;
+
+ enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+ swctrl-gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&bt_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&uart15 {
+ status = "okay";
+
+ /* Gamepad controlled by onboard MCU */
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1g_1p2>;
+ vccq-max-microamp = <1200000>;
+ vdd-hba-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "otg";
+ usb-role-switch;
+ maximum-speed = "super-speed-plus-gen2x1";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_dwc3_ss {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1e_0p88>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ phys = <&pm8550b_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l3f_0p88>;
+
+ orientation-switch;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy_dp_in {
+ remote-endpoint = <&mdss_dp0_out>;
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss_in>;
+};
+
+&usb_dp_qmpphy_usb_ss_in {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
--
2.44.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2024-04-24 15:29 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-04-24 15:29 [PATCH 00/10] AYN Odin 2 support Xilin Wu
2024-04-24 15:29 ` [PATCH 01/10] dt-bindings: pwm: Add SI-EN SN3112 PWM support Xilin Wu
2024-04-24 15:29 ` [PATCH 02/10] " Xilin Wu
2024-04-24 15:29 ` [PATCH 03/10] dt-bindings: display: panel: Add Synaptics TD4328 Xilin Wu
2024-04-24 15:29 ` [PATCH 04/10] drm/panel: Add driver for Synaptics TD4328 LCD panel Xilin Wu
2024-04-24 15:29 ` [PATCH 05/10] arm64: dts: qcom: pmk8550: Add PWM controller Xilin Wu
2024-04-24 15:29 ` [PATCH 06/10] arm64: dts: qcom: sm8550: Add UART15 Xilin Wu
2024-04-24 15:29 ` [PATCH 07/10] arm64: dts: qcom: sm8550: Update EAS properties Xilin Wu
2024-04-24 15:29 ` [PATCH 08/10] dt-bindings: vendor-prefixes: Add AYN Technologies Xilin Wu
2024-04-24 15:29 ` [PATCH 09/10] dt-bindings: arm: qcom: Add AYN Odin 2 Xilin Wu
2024-04-24 15:29 ` [PATCH 10/10] arm64: dts: " Xilin Wu
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