From: Krzysztof Adamski <k@japko.eu>
To: inus Walleij <linus.walleij@linaro.org>,
Maxime Ripard <maxime.ripard@free-electrons.com>,
Chen-Yu Tsai <wens@csie.org>, Hans de Goede <hdegoede@redhat.com>,
Lee Jones <lee@kernel.org>, Rob Herring <robh@kernel.org>,
Jens Kuske <jenskuske@gmail.com>,
Fabian Frederick <fabf@skynet.be>,
Vishnu Patekar <vishnupatekar0510@gmail.com>,
linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com
Cc: Krzysztof Adamski <k@japko.eu>
Subject: [PATCH v3 2/5] dts: sun8i-h3: Add APB0 related clocks and resets
Date: Thu, 4 Feb 2016 00:33:47 +0100 [thread overview]
Message-ID: <1454542430-16572-3-git-send-email-k@japko.eu> (raw)
In-Reply-To: <1454542430-16572-1-git-send-email-k@japko.eu>
APB0 is bearly mentioned in H3 User Manual and it is only setup in the
Allwinners kernel dump for CIR. I have verified experimentally that the
gate for R_PIO exists and works, though. There are probably other gates
there but I don't know their order right now and I don't have access to
their peripherals on my board to test them.
After some experiments and reviewing how this is organized on other
sunxi SoCs, I couldn't actually find any way to disable clocks for R_PIO
and they are working properly without doing anything so I assume they
are connected straight to the 24Mhz oscillator for now.
Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 1524130e..bb37f52 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -276,6 +276,24 @@
clocks = <&osc24M>, <&pll6 1>, <&pll5>;
clock-output-names = "mbus";
};
+
+ apb0: apb0_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&osc24M>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: clk@01f01428 {
+ compatible = "allwinner,sun8i-h3-apb0-gates-clk";
+ reg = <0x01f01428 0x4>;
+ #clock-cells = <1>;
+ clocks = <&apb0>;
+ clock-indices = <0>, <1>;
+ clock-output-names = "apb0_pio", "apb0_ir";
+ };
};
soc {
@@ -493,5 +511,11 @@
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ apb0_reset: reset@01f014b0 {
+ reg = <0x01f014b0 0x4>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
};
};
--
2.1.4
next prev parent reply other threads:[~2016-02-03 23:34 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-03 23:33 [PATCH v3 0/5] pinctrl: sunxi: Add H3 R_PIO controller support Krzysztof Adamski
2016-02-03 23:33 ` [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3 Krzysztof Adamski
2016-02-04 14:47 ` Jean-Francois Moine
2016-02-04 20:56 ` Krzysztof Adamski
2016-02-05 11:14 ` Maxime Ripard
2016-02-05 11:11 ` Maxime Ripard
2016-02-05 11:58 ` Krzysztof Adamski
2016-02-09 17:10 ` Maxime Ripard
2016-02-10 7:17 ` [linux-sunxi] " Krzysztof Adamski
2016-02-10 15:06 ` Maxime Ripard
2016-02-06 10:26 ` Jean-Francois Moine
2016-02-09 17:11 ` Maxime Ripard
2016-02-03 23:33 ` Krzysztof Adamski [this message]
2016-02-03 23:33 ` [PATCH v3 3/5] pinctrl: sunxi: Add H3 R_PIO controller support Krzysztof Adamski
2016-02-05 9:44 ` Chen-Yu Tsai
2016-02-05 9:46 ` Maxime Ripard
2016-02-03 23:33 ` [PATCH v3 4/5] ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi Krzysztof Adamski
2016-02-05 9:46 ` Chen-Yu Tsai
2016-02-08 8:39 ` Krzysztof Adamski
2016-02-03 23:33 ` [PATCH v3 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set Krzysztof Adamski
2016-02-05 9:45 ` Chen-Yu Tsai
2016-02-05 11:15 ` Maxime Ripard
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