* [RESEND PATCH v8 0/6] ARM: hisi: Add initial support including clock driver for Hi3519 soc.
@ 2016-02-05 2:31 Jiancheng Xue
2016-02-05 2:31 ` [RESEND PATCH v8 1/6] clk: hisilicon: add CRG driver for hi3519 soc Jiancheng Xue
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Jiancheng Xue @ 2016-02-05 2:31 UTC (permalink / raw)
To: mturquette, sboyd, p.zabel, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, khilman, arnd, olof, xuwei5,
haojian.zhuang, zhangfei.gao, bintian.wang
Cc: linux-kernel, linux-clk, devicetree, linux-arm-kernel, yanhaifeng,
yanghongwei, suwenping, raojun, ml.yang, gaofei, zhangzhenxing,
xuejiancheng, lidongpo, Jiancheng Xue
Hello,
Hi3519 soc is mainly used for ip camera and sport DV solutions. This patchset adds initial support
for Hi3519 soc. It includes clock driver, arch configuration, debug uart configuration and device tree.
It has been tested on hi3519 reference board.
Any comments will be appreciated!
Thanks!
Change Log
----------
v8:
--Made hi3519 clock driver can be compiled as a module
--Fixed an issue in arch/arm/Kconfig.debug
v7:
--Rebase to v4.5-rc1
v6:
-Change clock driver to a real platform driver
v5:
-Adjust clock and reset controller driver code
v4:
-Rebase to v4.4-rc7
-Divide patches according to Rob's comments
-Add spi nodes in hi3519-demb.dts
v3:
-Rebase to v4.4-rc4
-Adjust according to Arnd's comments
-Remove ARCH_HI3519, using ARCH_HISI directly
v2:
-Rebase to v4.4-rc3
-Put dt-binding doc and header file in a separate patch.
-Delete unused clocks definitions.
-Adjust the ARCH_xxx order in Kconfig file
-Rename ARCH_HI3xxx to ARCH_36xx
Jiancheng Xue (6):
clk: hisilicon: add CRG driver for hi3519 soc
ARM: hisi: add compatible string for Hi3519 soc
ARM: config: hisi: enable CONFIG_RESET_CONTROLLER
ARM: debug: add hi3519 debug uart
ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl
ARM: dts: add dts files for Hi3519
.../bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 ++
.../devicetree/bindings/clock/hi3519-crg.txt | 46 +++++
arch/arm/Kconfig.debug | 10 ++
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/hi3519-demb.dts | 42 +++++
arch/arm/boot/dts/hi3519.dtsi | 187 +++++++++++++++++++++
arch/arm/configs/hisi_defconfig | 1 +
arch/arm/mach-hisi/hisilicon.c | 23 +--
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile | 2 +
drivers/clk/hisilicon/clk-hi3519.c | 133 +++++++++++++++
drivers/clk/hisilicon/clk.c | 23 ++-
drivers/clk/hisilicon/clk.h | 14 +-
drivers/clk/hisilicon/reset.c | 130 ++++++++++++++
drivers/clk/hisilicon/reset.h | 32 ++++
include/dt-bindings/clock/hi3519-clock.h | 40 +++++
16 files changed, 672 insertions(+), 34 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
create mode 100644 arch/arm/boot/dts/hi3519-demb.dts
create mode 100644 arch/arm/boot/dts/hi3519.dtsi
create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
create mode 100644 drivers/clk/hisilicon/reset.c
create mode 100644 drivers/clk/hisilicon/reset.h
create mode 100644 include/dt-bindings/clock/hi3519-clock.h
--
1.9.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [RESEND PATCH v8 1/6] clk: hisilicon: add CRG driver for hi3519 soc
2016-02-05 2:31 [RESEND PATCH v8 0/6] ARM: hisi: Add initial support including clock driver for Hi3519 soc Jiancheng Xue
@ 2016-02-05 2:31 ` Jiancheng Xue
2016-02-17 0:46 ` Michael Turquette
2016-02-05 2:31 ` [RESEND PATCH v8 2/6] ARM: hisi: add compatible string for Hi3519 soc Jiancheng Xue
` (4 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: Jiancheng Xue @ 2016-02-05 2:31 UTC (permalink / raw)
To: mturquette, sboyd, p.zabel, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, khilman, arnd, olof, xuwei5,
haojian.zhuang, zhangfei.gao, bintian.wang
Cc: linux-kernel, linux-clk, devicetree, linux-arm-kernel, yanhaifeng,
yanghongwei, suwenping, raojun, ml.yang, gaofei, zhangzhenxing,
xuejiancheng, lidongpo, Jiancheng Xue
The CRG(Clock and Reset Generator) block provides clock
and reset signals for other modules in hi3519 soc.
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/clock/hi3519-crg.txt | 46 +++++++
This binding file is already acked by Rob Herring.
drivers/clk/hisilicon/Kconfig | 7 ++
drivers/clk/hisilicon/Makefile | 2 +
drivers/clk/hisilicon/clk-hi3519.c | 133 +++++++++++++++++++++
drivers/clk/hisilicon/clk.c | 23 ++--
drivers/clk/hisilicon/clk.h | 14 +--
drivers/clk/hisilicon/reset.c | 130 ++++++++++++++++++++
drivers/clk/hisilicon/reset.h | 32 +++++
include/dt-bindings/clock/hi3519-clock.h | 40 +++++++
9 files changed, 412 insertions(+), 15 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
create mode 100644 drivers/clk/hisilicon/reset.c
create mode 100644 drivers/clk/hisilicon/reset.h
create mode 100644 include/dt-bindings/clock/hi3519-clock.h
diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
new file mode 100644
index 0000000..2d23950
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
@@ -0,0 +1,46 @@
+* Hisilicon Hi3519 Clock and Reset Generator(CRG)
+
+The Hi3519 CRG module provides clock and reset signals to various
+controllers within the SoC.
+
+This binding uses the following bindings:
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+ Documentation/devicetree/bindings/reset/reset.txt
+
+Required Properties:
+
+- compatible: should be one of the following.
+ - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
+
+- #reset-cells: should be 2.
+
+A reset signal can be controlled by writing a bit register in the CRG module.
+The reset specifier consists of two cells. The first cell represents the
+register offset relative to the base address. The second cell represents the
+bit index in the register.
+
+Example: CRG nodes
+CRG: clock-reset-controller@12010000 {
+ compatible = "hisilicon,hi3519-crg";
+ reg = <0x12010000 0x10000>;
+ #clock-cells = <1>;
+ #reset-cells = <2>;
+};
+
+Example: consumer nodes
+i2c0: i2c@12110000 {
+ compatible = "hisilicon,hi3519-i2c";
+ reg = <0x12110000 0x1000>;
+ clocks = <&CRG HI3519_I2C0_RST>;*/
+ resets = <&CRG 0xe4 0>;
+};
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index e434854..2128899 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -1,3 +1,10 @@
+config COMMON_CLK_HI3519
+ tristate "Hi3519 Clock Driver"
+ depends on ARCH_HISI
+ default y
+ help
+ Build the clock driver for hi3519.
+
config COMMON_CLK_HI6220
bool "Hi6220 Clock Driver"
depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 74dba31..3f57b09 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -4,8 +4,10 @@
obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
+obj-$(CONFIG_RESET_CONTROLLER) += reset.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
+obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
new file mode 100644
index 0000000..ed983af
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3519.c
@@ -0,0 +1,133 @@
+/*
+ * Hi3519 Clock Driver
+ *
+ * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <dt-bindings/clock/hi3519-clock.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include "clk.h"
+#include "reset.h"
+
+#define HI3519_INNER_CLK_OFFSET 64
+#define HI3519_FIXED_24M 65
+#define HI3519_FIXED_50M 66
+#define HI3519_FIXED_75M 67
+#define HI3519_FIXED_125M 68
+#define HI3519_FIXED_150M 69
+#define HI3519_FIXED_200M 70
+#define HI3519_FIXED_250M 71
+#define HI3519_FIXED_300M 72
+#define HI3519_FIXED_400M 73
+#define HI3519_FMC_MUX 74
+
+#define HI3519_NR_CLKS 128
+
+static const struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] = {
+ { HI3519_FIXED_24M, "24m", NULL, CLK_IS_ROOT, 24000000, },
+ { HI3519_FIXED_50M, "50m", NULL, CLK_IS_ROOT, 50000000, },
+ { HI3519_FIXED_75M, "75m", NULL, CLK_IS_ROOT, 75000000, },
+ { HI3519_FIXED_125M, "125m", NULL, CLK_IS_ROOT, 125000000, },
+ { HI3519_FIXED_150M, "150m", NULL, CLK_IS_ROOT, 150000000, },
+ { HI3519_FIXED_200M, "200m", NULL, CLK_IS_ROOT, 200000000, },
+ { HI3519_FIXED_250M, "250m", NULL, CLK_IS_ROOT, 250000000, },
+ { HI3519_FIXED_300M, "300m", NULL, CLK_IS_ROOT, 300000000, },
+ { HI3519_FIXED_400M, "400m", NULL, CLK_IS_ROOT, 400000000, },
+};
+
+static const char *const fmc_mux_p[] = {
+ "24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", };
+static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
+
+static const struct hisi_mux_clock hi3519_mux_clks[] = {
+ { HI3519_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
+ CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
+};
+
+static const struct hisi_gate_clock hi3519_gate_clks[] = {
+ { HI3519_FMC_CLK, "clk_fmc", "fmc_mux",
+ CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
+ { HI3519_UART0_CLK, "clk_uart0", "24m",
+ CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
+ { HI3519_UART1_CLK, "clk_uart1", "24m",
+ CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
+ { HI3519_UART2_CLK, "clk_uart2", "24m",
+ CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
+ { HI3519_UART3_CLK, "clk_uart3", "24m",
+ CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
+ { HI3519_UART4_CLK, "clk_uart4", "24m",
+ CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
+ { HI3519_SPI0_CLK, "clk_spi0", "50m",
+ CLK_SET_RATE_PARENT, 0xe4, 16, 0, },
+ { HI3519_SPI1_CLK, "clk_spi1", "50m",
+ CLK_SET_RATE_PARENT, 0xe4, 17, 0, },
+ { HI3519_SPI2_CLK, "clk_spi2", "50m",
+ CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
+};
+
+static int hi3519_clk_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct hisi_clock_data *clk_data;
+
+ clk_data = hisi_clk_init(np, HI3519_NR_CLKS);
+ if (!clk_data)
+ return -ENODEV;
+
+ hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
+ ARRAY_SIZE(hi3519_fixed_rate_clks),
+ clk_data);
+ hisi_clk_register_mux(hi3519_mux_clks, ARRAY_SIZE(hi3519_mux_clks),
+ clk_data);
+ hisi_clk_register_gate(hi3519_gate_clks,
+ ARRAY_SIZE(hi3519_gate_clks), clk_data);
+
+ return hisi_reset_init(np);
+}
+
+static const struct of_device_id hi3519_clk_match_table[] = {
+ { .compatible = "hisilicon,hi3519-crg" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, hi3519_clk_match_table);
+
+static struct platform_driver hi3519_clk_driver = {
+ .probe = hi3519_clk_probe,
+ .driver = {
+ .name = "hi3519-clk",
+ .of_match_table = hi3519_clk_match_table,
+ },
+};
+
+static int __init hi3519_clk_init(void)
+{
+ return platform_driver_register(&hi3519_clk_driver);
+}
+core_initcall(hi3519_clk_init);
+
+static void __exit hi3519_clk_exit(void)
+{
+ platform_driver_unregister(&hi3519_clk_driver);
+}
+module_exit(hi3519_clk_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("HiSilicon Hi3519 Clock Driver");
diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c
index 9f8e766..06ec3fe 100644
--- a/drivers/clk/hisilicon/clk.c
+++ b/drivers/clk/hisilicon/clk.c
@@ -37,7 +37,7 @@
static DEFINE_SPINLOCK(hisi_clk_lock);
-struct hisi_clock_data __init *hisi_clk_init(struct device_node *np,
+struct hisi_clock_data *hisi_clk_init(struct device_node *np,
int nr_clks)
{
struct hisi_clock_data *clk_data;
@@ -71,8 +71,9 @@ err_data:
err:
return NULL;
}
+EXPORT_SYMBOL(hisi_clk_init);
-void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks,
+void hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks,
int nums, struct hisi_clock_data *data)
{
struct clk *clk;
@@ -91,8 +92,9 @@ void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks,
data->clk_data.clks[clks[i].id] = clk;
}
}
+EXPORT_SYMBOL(hisi_clk_register_fixed_rate);
-void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks,
+void hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks,
int nums,
struct hisi_clock_data *data)
{
@@ -112,8 +114,9 @@ void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks,
data->clk_data.clks[clks[i].id] = clk;
}
}
+EXPORT_SYMBOL(hisi_clk_register_fixed_factor);
-void __init hisi_clk_register_mux(struct hisi_mux_clock *clks,
+void hisi_clk_register_mux(const struct hisi_mux_clock *clks,
int nums, struct hisi_clock_data *data)
{
struct clk *clk;
@@ -141,8 +144,9 @@ void __init hisi_clk_register_mux(struct hisi_mux_clock *clks,
data->clk_data.clks[clks[i].id] = clk;
}
}
+EXPORT_SYMBOL(hisi_clk_register_mux);
-void __init hisi_clk_register_divider(struct hisi_divider_clock *clks,
+void hisi_clk_register_divider(const struct hisi_divider_clock *clks,
int nums, struct hisi_clock_data *data)
{
struct clk *clk;
@@ -170,8 +174,9 @@ void __init hisi_clk_register_divider(struct hisi_divider_clock *clks,
data->clk_data.clks[clks[i].id] = clk;
}
}
+EXPORT_SYMBOL(hisi_clk_register_divider);
-void __init hisi_clk_register_gate(struct hisi_gate_clock *clks,
+void hisi_clk_register_gate(const struct hisi_gate_clock *clks,
int nums, struct hisi_clock_data *data)
{
struct clk *clk;
@@ -198,8 +203,9 @@ void __init hisi_clk_register_gate(struct hisi_gate_clock *clks,
data->clk_data.clks[clks[i].id] = clk;
}
}
+EXPORT_SYMBOL(hisi_clk_register_gate);
-void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks,
+void hisi_clk_register_gate_sep(const struct hisi_gate_clock *clks,
int nums, struct hisi_clock_data *data)
{
struct clk *clk;
@@ -226,8 +232,9 @@ void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks,
data->clk_data.clks[clks[i].id] = clk;
}
}
+EXPORT_SYMBOL(hisi_clk_register_gate_sep);
-void __init hi6220_clk_register_divider(struct hi6220_divider_clock *clks,
+void __init hi6220_clk_register_divider(const struct hi6220_divider_clock *clks,
int nums, struct hisi_clock_data *data)
{
struct clk *clk;
diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h
index b56fbc1..20d64af 100644
--- a/drivers/clk/hisilicon/clk.h
+++ b/drivers/clk/hisilicon/clk.h
@@ -111,18 +111,18 @@ struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
u8 shift, u8 width, u32 mask_bit, spinlock_t *lock);
struct hisi_clock_data *hisi_clk_init(struct device_node *, int);
-void hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *,
+void hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *,
int, struct hisi_clock_data *);
-void hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *,
+void hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *,
int, struct hisi_clock_data *);
-void hisi_clk_register_mux(struct hisi_mux_clock *, int,
+void hisi_clk_register_mux(const struct hisi_mux_clock *, int,
struct hisi_clock_data *);
-void hisi_clk_register_divider(struct hisi_divider_clock *,
+void hisi_clk_register_divider(const struct hisi_divider_clock *,
int, struct hisi_clock_data *);
-void hisi_clk_register_gate(struct hisi_gate_clock *,
+void hisi_clk_register_gate(const struct hisi_gate_clock *,
int, struct hisi_clock_data *);
-void hisi_clk_register_gate_sep(struct hisi_gate_clock *,
+void hisi_clk_register_gate_sep(const struct hisi_gate_clock *,
int, struct hisi_clock_data *);
-void hi6220_clk_register_divider(struct hi6220_divider_clock *,
+void hi6220_clk_register_divider(const struct hi6220_divider_clock *,
int, struct hisi_clock_data *);
#endif /* __HISI_CLK_H */
diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c
new file mode 100644
index 0000000..4fc7c8f
--- /dev/null
+++ b/drivers/clk/hisilicon/reset.c
@@ -0,0 +1,130 @@
+/*
+ * Hisilicon Reset Controller Driver
+ *
+ * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#define HISI_RESET_BIT_MASK 0x1f
+#define HISI_RESET_OFFSET_SHIFT 8
+#define HISI_RESET_OFFSET_MASK 0xffff00
+
+struct hisi_reset_controller {
+ spinlock_t lock;
+ void __iomem *membase;
+ struct reset_controller_dev rcdev;
+};
+
+
+#define to_hisi_reset_controller(rcdev) \
+ container_of(rcdev, struct hisi_reset_controller, rcdev)
+
+static int hisi_reset_of_xlate(struct reset_controller_dev *rcdev,
+ const struct of_phandle_args *reset_spec)
+{
+ u32 offset;
+ u8 bit;
+
+ if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
+ return -EINVAL;
+
+ offset = (reset_spec->args[0] << HISI_RESET_OFFSET_SHIFT)
+ & HISI_RESET_OFFSET_MASK;
+ bit = reset_spec->args[1] & HISI_RESET_BIT_MASK;
+ return (offset | bit);
+}
+
+static int hisi_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct hisi_reset_controller *rstc = to_hisi_reset_controller(rcdev);
+ unsigned long flags;
+ u32 offset, reg;
+ u8 bit;
+
+ offset = (id & HISI_RESET_OFFSET_MASK) >> HISI_RESET_OFFSET_SHIFT;
+ bit = id & HISI_RESET_BIT_MASK;
+
+ spin_lock_irqsave(&rstc->lock, flags);
+
+ reg = readl(rstc->membase + offset);
+ writel(reg | BIT(bit), rstc->membase + offset);
+
+ spin_unlock_irqrestore(&rstc->lock, flags);
+
+ return 0;
+}
+
+static int hisi_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct hisi_reset_controller *rstc = to_hisi_reset_controller(rcdev);
+ unsigned long flags;
+ u32 offset, reg;
+ u8 bit;
+
+ offset = (id & HISI_RESET_OFFSET_MASK) >> HISI_RESET_OFFSET_SHIFT;
+ bit = id & HISI_RESET_BIT_MASK;
+
+ spin_lock_irqsave(&rstc->lock, flags);
+
+ reg = readl(rstc->membase + offset);
+ writel(reg & ~BIT(bit), rstc->membase + offset);
+
+ spin_unlock_irqrestore(&rstc->lock, flags);
+
+ return 0;
+}
+
+static struct reset_control_ops hisi_reset_ops = {
+ .assert = hisi_reset_assert,
+ .deassert = hisi_reset_deassert,
+};
+
+int hisi_reset_init(struct device_node *np)
+{
+ struct hisi_reset_controller *rstc;
+
+ rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
+ if (!rstc)
+ return -ENOMEM;
+
+ rstc->membase = of_iomap(np, 0);
+ if (!rstc->membase)
+ return -EINVAL;
+
+ spin_lock_init(&rstc->lock);
+
+ rstc->rcdev.owner = THIS_MODULE;
+ rstc->rcdev.ops = &hisi_reset_ops;
+ rstc->rcdev.of_node = np;
+ rstc->rcdev.of_reset_n_cells = 2;
+ rstc->rcdev.of_xlate = hisi_reset_of_xlate;
+
+ return reset_controller_register(&rstc->rcdev);
+}
+EXPORT_SYMBOL(hisi_reset_init);
diff --git a/drivers/clk/hisilicon/reset.h b/drivers/clk/hisilicon/reset.h
new file mode 100644
index 0000000..ffad4d7
--- /dev/null
+++ b/drivers/clk/hisilicon/reset.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __HISI_RESET_H
+#define __HISI_RESET_H
+
+struct device_node;
+
+#ifdef CONFIG_RESET_CONTROLLER
+int hisi_reset_init(struct device_node *np);
+#else
+static inline int hisi_reset_init(struct device_node *np)
+{
+ return 0;
+}
+#endif
+
+#endif /* __HISI_RESET_H */
diff --git a/include/dt-bindings/clock/hi3519-clock.h b/include/dt-bindings/clock/hi3519-clock.h
new file mode 100644
index 0000000..4989c80
--- /dev/null
+++ b/include/dt-bindings/clock/hi3519-clock.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HI3519_CLOCK_H
+#define __DTS_HI3519_CLOCK_H
+
+#define HI3519_FMC_CLK 1
+#define HI3519_USB2_BUS_CLK 2
+#define HI3519_USB2_PORT_CLK 3
+#define HI3519_USB3_CLK 4
+#define HI3519_ETH_PHY_CLK 5
+#define HI3519_ETH_MAC_CLK 6
+#define HI3519_ETH_MACIF_CLK 7
+#define HI3519_PWM_CLK 8
+#define HI3519_DMA_CLK 9
+#define HI3519_SPI0_CLK 10
+#define HI3519_SPI1_CLK 11
+#define HI3519_SPI2_CLK 12
+#define HI3519_IR_CLK 13
+#define HI3519_UART0_CLK 14
+#define HI3519_UART1_CLK 15
+#define HI3519_UART2_CLK 16
+#define HI3519_UART3_CLK 17
+#define HI3519_UART4_CLK 18
+
+#endif /* __DTS_HI3519_CLOCK_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [RESEND PATCH v8 2/6] ARM: hisi: add compatible string for Hi3519 soc
2016-02-05 2:31 [RESEND PATCH v8 0/6] ARM: hisi: Add initial support including clock driver for Hi3519 soc Jiancheng Xue
2016-02-05 2:31 ` [RESEND PATCH v8 1/6] clk: hisilicon: add CRG driver for hi3519 soc Jiancheng Xue
@ 2016-02-05 2:31 ` Jiancheng Xue
2016-02-05 2:31 ` [RESEND PATCH v8 3/6] ARM: config: hisi: enable CONFIG_RESET_CONTROLLER Jiancheng Xue
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Jiancheng Xue @ 2016-02-05 2:31 UTC (permalink / raw)
To: mturquette, sboyd, p.zabel, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, khilman, arnd, olof, xuwei5,
haojian.zhuang, zhangfei.gao, bintian.wang
Cc: linux-kernel, linux-clk, devicetree, linux-arm-kernel, yanhaifeng,
yanghongwei, suwenping, raojun, ml.yang, gaofei, zhangzhenxing,
xuejiancheng, lidongpo, Jiancheng Xue
add compatible string for Hi3519 soc.
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
arch/arm/mach-hisi/hisilicon.c | 23 ++++-------------------
1 file changed, 4 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
index 8cc6215..00dae89 100644
--- a/arch/arm/mach-hisi/hisilicon.c
+++ b/arch/arm/mach-hisi/hisilicon.c
@@ -54,30 +54,15 @@ DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
.dt_compat = hi3xxx_compat,
MACHINE_END
-static const char *const hix5hd2_compat[] __initconst = {
+static const char *const hisilicon_compat[] __initconst = {
"hisilicon,hix5hd2",
- NULL,
-};
-
-DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)")
- .dt_compat = hix5hd2_compat,
-MACHINE_END
-
-static const char *const hip04_compat[] __initconst = {
"hisilicon,hip04-d01",
- NULL,
-};
-
-DT_MACHINE_START(HIP04, "Hisilicon HiP04 (Flattened Device Tree)")
- .dt_compat = hip04_compat,
-MACHINE_END
-
-static const char *const hip01_compat[] __initconst = {
"hisilicon,hip01",
"hisilicon,hip01-ca9x2",
+ "hisilicon,hi3519",
NULL,
};
-DT_MACHINE_START(HIP01, "Hisilicon HIP01 (Flattened Device Tree)")
- .dt_compat = hip01_compat,
+DT_MACHINE_START(HISILICON_DT, "HiSilicon Soc")
+ .dt_compat = hisilicon_compat,
MACHINE_END
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [RESEND PATCH v8 3/6] ARM: config: hisi: enable CONFIG_RESET_CONTROLLER
2016-02-05 2:31 [RESEND PATCH v8 0/6] ARM: hisi: Add initial support including clock driver for Hi3519 soc Jiancheng Xue
2016-02-05 2:31 ` [RESEND PATCH v8 1/6] clk: hisilicon: add CRG driver for hi3519 soc Jiancheng Xue
2016-02-05 2:31 ` [RESEND PATCH v8 2/6] ARM: hisi: add compatible string for Hi3519 soc Jiancheng Xue
@ 2016-02-05 2:31 ` Jiancheng Xue
2016-02-05 2:31 ` [RESEND PATCH v8 4/6] ARM: debug: add hi3519 debug uart Jiancheng Xue
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Jiancheng Xue @ 2016-02-05 2:31 UTC (permalink / raw)
To: mturquette, sboyd, p.zabel, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, khilman, arnd, olof, xuwei5,
haojian.zhuang, zhangfei.gao, bintian.wang
Cc: linux-kernel, linux-clk, devicetree, linux-arm-kernel, yanhaifeng,
yanghongwei, suwenping, raojun, ml.yang, gaofei, zhangzhenxing,
xuejiancheng, lidongpo, Jiancheng Xue
enable CONFIG_RESET_CONTROLLER in hisi_defconfig
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
arch/arm/configs/hisi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig
index b2e340b..ba62c07 100644
--- a/arch/arm/configs/hisi_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -75,6 +75,7 @@ CONFIG_DMADEVICES=y
CONFIG_DW_DMAC=y
CONFIG_PL330_DMA=y
CONFIG_PWM=y
+CONFIG_RESET_CONTROLLER=y
CONFIG_PHY_HIX5HD2_SATA=y
CONFIG_EXT4_FS=y
CONFIG_TMPFS=y
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [RESEND PATCH v8 4/6] ARM: debug: add hi3519 debug uart
2016-02-05 2:31 [RESEND PATCH v8 0/6] ARM: hisi: Add initial support including clock driver for Hi3519 soc Jiancheng Xue
` (2 preceding siblings ...)
2016-02-05 2:31 ` [RESEND PATCH v8 3/6] ARM: config: hisi: enable CONFIG_RESET_CONTROLLER Jiancheng Xue
@ 2016-02-05 2:31 ` Jiancheng Xue
2016-02-05 2:31 ` [RESEND PATCH v8 5/6] ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl Jiancheng Xue
2016-02-05 2:31 ` [RESEND PATCH v8 6/6] ARM: dts: add dts files for Hi3519 Jiancheng Xue
5 siblings, 0 replies; 9+ messages in thread
From: Jiancheng Xue @ 2016-02-05 2:31 UTC (permalink / raw)
To: mturquette, sboyd, p.zabel, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, khilman, arnd, olof, xuwei5,
haojian.zhuang, zhangfei.gao, bintian.wang
Cc: linux-kernel, linux-clk, devicetree, linux-arm-kernel, yanhaifeng,
yanghongwei, suwenping, raojun, ml.yang, gaofei, zhangzhenxing,
xuejiancheng, lidongpo, Jiancheng Xue
add hi3519 debug uart
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
arch/arm/Kconfig.debug | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index c6b6175..edd3fbe 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -260,6 +260,14 @@ choice
Say Y here if you want kernel low-level debugging support
on Cortina Gemini based platforms.
+ config DEBUG_HI3519_UART
+ bool "Hisilicon HI3519 Debug UART"
+ depends on ARCH_HISI
+ select DEBUG_UART_PL01X
+ help
+ Say Y here if you want kernel low-level debugging support
+ on HI3519 UART.
+
config DEBUG_HI3620_UART
bool "Hisilicon HI3620 Debug UART"
depends on ARCH_HI3xxx
@@ -1451,6 +1459,7 @@ config DEBUG_UART_PHYS
default 0x11002000 if DEBUG_MT8127_UART0
default 0x11006000 if DEBUG_MT6589_UART0
default 0x11009000 if DEBUG_MT8135_UART3
+ default 0x12100000 if DEBUG_HI3519_UART
default 0x16000000 if DEBUG_INTEGRATOR
default 0x18000300 if DEBUG_BCM_5301X
default 0x18010000 if DEBUG_SIRFATLAS7_UART0
@@ -1619,6 +1628,7 @@ config DEBUG_UART_VIRT
default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
default 0xfee82340 if ARCH_IOP13XX
default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
+ default 0xfef00000 if DEBUG_HI3519_UART
default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
default 0xfef36000 if DEBUG_HIGHBANK_UART
default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [RESEND PATCH v8 5/6] ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl
2016-02-05 2:31 [RESEND PATCH v8 0/6] ARM: hisi: Add initial support including clock driver for Hi3519 soc Jiancheng Xue
` (3 preceding siblings ...)
2016-02-05 2:31 ` [RESEND PATCH v8 4/6] ARM: debug: add hi3519 debug uart Jiancheng Xue
@ 2016-02-05 2:31 ` Jiancheng Xue
2016-02-05 2:31 ` [RESEND PATCH v8 6/6] ARM: dts: add dts files for Hi3519 Jiancheng Xue
5 siblings, 0 replies; 9+ messages in thread
From: Jiancheng Xue @ 2016-02-05 2:31 UTC (permalink / raw)
To: mturquette, sboyd, p.zabel, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, khilman, arnd, olof, xuwei5,
haojian.zhuang, zhangfei.gao, bintian.wang
Cc: linux-kernel, linux-clk, devicetree, linux-arm-kernel, yanhaifeng,
yanghongwei, suwenping, raojun, ml.yang, gaofei, zhangzhenxing,
xuejiancheng, lidongpo, Jiancheng Xue
Add device tree bindings for Hi3519 system controller.
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
new file mode 100644
index 0000000..115c5be
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
@@ -0,0 +1,14 @@
+* Hisilicon Hi3519 System Controller Block
+
+This bindings use the following binding:
+Documentation/devicetree/bindings/mfd/syscon.txt
+
+Required properties:
+- compatible: "hisilicon,hi3519-sysctrl".
+- reg: the register region of this block
+
+Examples:
+sysctrl: system-controller@12010000 {
+ compatible = "hisilicon,hi3519-sysctrl", "syscon";
+ reg = <0x12010000 0x1000>;
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [RESEND PATCH v8 6/6] ARM: dts: add dts files for Hi3519
2016-02-05 2:31 [RESEND PATCH v8 0/6] ARM: hisi: Add initial support including clock driver for Hi3519 soc Jiancheng Xue
` (4 preceding siblings ...)
2016-02-05 2:31 ` [RESEND PATCH v8 5/6] ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl Jiancheng Xue
@ 2016-02-05 2:31 ` Jiancheng Xue
5 siblings, 0 replies; 9+ messages in thread
From: Jiancheng Xue @ 2016-02-05 2:31 UTC (permalink / raw)
To: mturquette, sboyd, p.zabel, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, khilman, arnd, olof, xuwei5,
haojian.zhuang, zhangfei.gao, bintian.wang
Cc: linux-kernel, linux-clk, devicetree, linux-arm-kernel, yanhaifeng,
yanghongwei, suwenping, raojun, ml.yang, gaofei, zhangzhenxing,
xuejiancheng, lidongpo, Jiancheng Xue
add dts files for Hi3519
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/hi3519-demb.dts | 42 +++++++++
arch/arm/boot/dts/hi3519.dtsi | 187 ++++++++++++++++++++++++++++++++++++++
3 files changed, 231 insertions(+)
create mode 100644 arch/arm/boot/dts/hi3519-demb.dts
create mode 100644 arch/arm/boot/dts/hi3519.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a4a6d70..3ce36ff 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -141,6 +141,8 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
exynos5800-peach-pi.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += \
hi3620-hi4511.dtb
+dtb-$(CONFIG_ARCH_HISI) += \
+ hi3519-demb.dtb
dtb-$(CONFIG_ARCH_HIX5HD2) += \
hisi-x5hd2-dkb.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += \
diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts
new file mode 100644
index 0000000..6991ab6
--- /dev/null
+++ b/arch/arm/boot/dts/hi3519-demb.dts
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+/dts-v1/;
+#include "hi3519.dtsi"
+
+/ {
+ model = "HiSilicon HI3519 DEMO Board";
+ compatible = "hisilicon,hi3519";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&dual_timer0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi
new file mode 100644
index 0000000..5729ecf
--- /dev/null
+++ b/arch/arm/boot/dts/hi3519.dtsi
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <dt-bindings/clock/hi3519-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chosen { };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ };
+ };
+
+ gic: interrupt-controller@10300000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
+ };
+
+ clk_3m: clk_3m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <3000000>;
+ };
+
+ crg: clock-reset-controller@12010000 {
+ compatible = "hisilicon,hi3519-crg";
+ #clock-cells = <1>;
+ #reset-cells = <2>;
+ reg = <0x12010000 0x10000>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ uart0: serial@12100000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12100000 0x1000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HI3519_UART0_CLK>;
+ clock-names = "apb_pclk";
+ status = "disable";
+ };
+
+ uart1: serial@12101000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12101000 0x1000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HI3519_UART1_CLK>;
+ clock-names = "apb_pclk";
+ status = "disable";
+ };
+
+ uart2: serial@12102000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12102000 0x1000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HI3519_UART2_CLK>;
+ clock-names = "apb_pclk";
+ status = "disable";
+ };
+
+ uart3: serial@12103000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12103000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HI3519_UART3_CLK>;
+ clock-names = "apb_pclk";
+ status = "disable";
+ };
+
+ uart4: serial@12104000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12104000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HI3519_UART4_CLK>;
+ clock-names = "apb_pclk";
+ status = "disable";
+ };
+
+ dual_timer0: timer@12000000 {
+ compatible = "arm,sp804", "arm,primecell";
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x12000000 0x1000>;
+ clocks = <&clk_3m>;
+ clock-names = "apb_pclk";
+ status = "disable";
+ };
+
+ dual_timer1: timer@12001000 {
+ compatible = "arm,sp804", "arm,primecell";
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x12001000 0x1000>;
+ clocks = <&clk_3m>;
+ clock-names = "apb_pclk";
+ status = "disable";
+ };
+
+ dual_timer2: timer@12002000 {
+ compatible = "arm,sp804", "arm,primecell";
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x12002000 0x1000>;
+ clocks = <&clk_3m>;
+ clock-names = "apb_pclk";
+ status = "disable";
+ };
+
+ spi_bus0: spi@12120000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x12120000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HI3519_SPI0_CLK>;
+ clock-names = "apb_pclk";
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disable";
+ };
+
+ spi_bus1: spi@12121000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x12121000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HI3519_SPI1_CLK>;
+ clock-names = "apb_pclk";
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disable";
+ };
+
+ spi_bus2: spi@12122000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x12122000 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HI3519_SPI2_CLK>;
+ clock-names = "apb_pclk";
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disable";
+ };
+
+ sysctrl: system-controller@12020000 {
+ compatible = "hisilicon,hi3519-sysctrl", "syscon";
+ reg = <0x12020000 0x1000>;
+ };
+
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&sysctrl>;
+ offset = <0x4>;
+ mask = <0xdeadbeef>;
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [RESEND PATCH v8 1/6] clk: hisilicon: add CRG driver for hi3519 soc
2016-02-05 2:31 ` [RESEND PATCH v8 1/6] clk: hisilicon: add CRG driver for hi3519 soc Jiancheng Xue
@ 2016-02-17 0:46 ` Michael Turquette
2016-02-17 3:08 ` xuejiancheng
0 siblings, 1 reply; 9+ messages in thread
From: Michael Turquette @ 2016-02-17 0:46 UTC (permalink / raw)
To: Jiancheng Xue, sboyd, p.zabel, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, khilman, arnd, olof, xuwei5,
haojian.zhuang, zhangfei.gao, bintian.wang
Cc: linux-kernel, linux-clk, devicetree, linux-arm-kernel, yanhaifeng,
yanghongwei, suwenping, raojun, ml.yang, gaofei, zhangzhenxing,
xuejiancheng, lidongpo, Jiancheng Xue
Hello Jiancheng Xue,
Quoting Jiancheng Xue (2016-02-04 18:31:07)
> diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
> index 74dba31..3f57b09 100644
> --- a/drivers/clk/hisilicon/Makefile
> +++ b/drivers/clk/hisilicon/Makefile
> @@ -4,8 +4,10 @@
>
> obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
>
> +obj-$(CONFIG_RESET_CONTROLLER) += reset.o
Do you really want to build reset.o for all hisi SoCs?
> obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
> obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
> obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
> obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
> obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
> +obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
> diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
> new file mode 100644
> index 0000000..ed983af
> --- /dev/null
> +++ b/drivers/clk/hisilicon/clk-hi3519.c
> @@ -0,0 +1,133 @@
> +/*
> + * Hi3519 Clock Driver
> + *
> + * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <dt-bindings/clock/hi3519-clock.h>
> +#include <linux/delay.h>
Remove this header.
> +#include <linux/module.h>
> +#include <linux/of_address.h>
Remove this header.
> +#include <linux/of_platform.h>
Remove this header.
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
Remove this header.
> diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c
> index 9f8e766..06ec3fe 100644
> --- a/drivers/clk/hisilicon/clk.c
> +++ b/drivers/clk/hisilicon/clk.c
> @@ -37,7 +37,7 @@
>
> static DEFINE_SPINLOCK(hisi_clk_lock);
>
> -struct hisi_clock_data __init *hisi_clk_init(struct device_node *np,
> +struct hisi_clock_data *hisi_clk_init(struct device_node *np,
> int nr_clks)
> {
> struct hisi_clock_data *clk_data;
> @@ -71,8 +71,9 @@ err_data:
> err:
> return NULL;
> }
> +EXPORT_SYMBOL(hisi_clk_init);
>
> -void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks,
> +void hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks,
> int nums, struct hisi_clock_data *data)
> {
> struct clk *clk;
> @@ -91,8 +92,9 @@ void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks,
> data->clk_data.clks[clks[i].id] = clk;
> }
> }
> +EXPORT_SYMBOL(hisi_clk_register_fixed_rate);
>
> -void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks,
> +void hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks,
> int nums,
> struct hisi_clock_data *data)
> {
> @@ -112,8 +114,9 @@ void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks,
> data->clk_data.clks[clks[i].id] = clk;
> }
> }
> +EXPORT_SYMBOL(hisi_clk_register_fixed_factor);
>
> -void __init hisi_clk_register_mux(struct hisi_mux_clock *clks,
> +void hisi_clk_register_mux(const struct hisi_mux_clock *clks,
> int nums, struct hisi_clock_data *data)
> {
> struct clk *clk;
> @@ -141,8 +144,9 @@ void __init hisi_clk_register_mux(struct hisi_mux_clock *clks,
> data->clk_data.clks[clks[i].id] = clk;
> }
> }
> +EXPORT_SYMBOL(hisi_clk_register_mux);
>
> -void __init hisi_clk_register_divider(struct hisi_divider_clock *clks,
> +void hisi_clk_register_divider(const struct hisi_divider_clock *clks,
> int nums, struct hisi_clock_data *data)
> {
> struct clk *clk;
> @@ -170,8 +174,9 @@ void __init hisi_clk_register_divider(struct hisi_divider_clock *clks,
> data->clk_data.clks[clks[i].id] = clk;
> }
> }
> +EXPORT_SYMBOL(hisi_clk_register_divider);
>
> -void __init hisi_clk_register_gate(struct hisi_gate_clock *clks,
> +void hisi_clk_register_gate(const struct hisi_gate_clock *clks,
> int nums, struct hisi_clock_data *data)
> {
> struct clk *clk;
> @@ -198,8 +203,9 @@ void __init hisi_clk_register_gate(struct hisi_gate_clock *clks,
> data->clk_data.clks[clks[i].id] = clk;
> }
> }
> +EXPORT_SYMBOL(hisi_clk_register_gate);
>
> -void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks,
> +void hisi_clk_register_gate_sep(const struct hisi_gate_clock *clks,
> int nums, struct hisi_clock_data *data)
> {
> struct clk *clk;
> @@ -226,8 +232,9 @@ void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks,
> data->clk_data.clks[clks[i].id] = clk;
> }
> }
> +EXPORT_SYMBOL(hisi_clk_register_gate_sep);
>
> -void __init hi6220_clk_register_divider(struct hi6220_divider_clock *clks,
> +void __init hi6220_clk_register_divider(const struct hi6220_divider_clock *clks,
> int nums, struct hisi_clock_data *data)
It would have been better to break out all of the changes to clk.c into
a separate patch.
> {
> struct clk *clk;
> diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h
> index b56fbc1..20d64af 100644
> --- a/drivers/clk/hisilicon/clk.h
> +++ b/drivers/clk/hisilicon/clk.h
> @@ -111,18 +111,18 @@ struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
> u8 shift, u8 width, u32 mask_bit, spinlock_t *lock);
>
> struct hisi_clock_data *hisi_clk_init(struct device_node *, int);
> -void hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *,
> +void hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *,
> int, struct hisi_clock_data *);
> -void hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *,
> +void hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *,
> int, struct hisi_clock_data *);
> -void hisi_clk_register_mux(struct hisi_mux_clock *, int,
> +void hisi_clk_register_mux(const struct hisi_mux_clock *, int,
> struct hisi_clock_data *);
> -void hisi_clk_register_divider(struct hisi_divider_clock *,
> +void hisi_clk_register_divider(const struct hisi_divider_clock *,
> int, struct hisi_clock_data *);
> -void hisi_clk_register_gate(struct hisi_gate_clock *,
> +void hisi_clk_register_gate(const struct hisi_gate_clock *,
> int, struct hisi_clock_data *);
> -void hisi_clk_register_gate_sep(struct hisi_gate_clock *,
> +void hisi_clk_register_gate_sep(const struct hisi_gate_clock *,
> int, struct hisi_clock_data *);
> -void hi6220_clk_register_divider(struct hi6220_divider_clock *,
> +void hi6220_clk_register_divider(const struct hi6220_divider_clock *,
> int, struct hisi_clock_data *);
> #endif /* __HISI_CLK_H */
Ditto.
> diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c
> new file mode 100644
> index 0000000..4fc7c8f
> --- /dev/null
> +++ b/drivers/clk/hisilicon/reset.c
> @@ -0,0 +1,130 @@
> +/*
> + * Hisilicon Reset Controller Driver
> + *
> + * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +#include <linux/types.h>
I didn't look into these headers but I'm guessing they aren't all
needed?
Best regards,
Mike
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RESEND PATCH v8 1/6] clk: hisilicon: add CRG driver for hi3519 soc
2016-02-17 0:46 ` Michael Turquette
@ 2016-02-17 3:08 ` xuejiancheng
0 siblings, 0 replies; 9+ messages in thread
From: xuejiancheng @ 2016-02-17 3:08 UTC (permalink / raw)
To: Michael Turquette, sboyd, p.zabel, robh+dt, pawel.moll,
mark.rutland, ijc+devicetree, galak, linux, khilman, arnd, olof,
xuwei5, haojian.zhuang, zhangfei.gao, bintian.wang
Cc: linux-kernel, linux-clk, devicetree, linux-arm-kernel, yanhaifeng,
yanghongwei, suwenping, raojun, ml.yang, gaofei, zhangzhenxing,
xuejiancheng, lidongpo
Hi Mike,
Thank you very much for your comments.
On 2016/2/17 8:46, Michael Turquette wrote:
> Hello Jiancheng Xue,
>
> Quoting Jiancheng Xue (2016-02-04 18:31:07)
>> diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
>> index 74dba31..3f57b09 100644
>> --- a/drivers/clk/hisilicon/Makefile
>> +++ b/drivers/clk/hisilicon/Makefile
>> @@ -4,8 +4,10 @@
>>
>> obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
>>
>> +obj-$(CONFIG_RESET_CONTROLLER) += reset.o
>
> Do you really want to build reset.o for all hisi SoCs?
>
This reset controller driver will be just used in some of hisilicon SOCs.
I'll add a specific config item for it like CONFIG_RESET_HISI. The config
item will be selected by default in SOCs needing this driver.
I'll also fix other issues in next version. Thank you!
Regards,
Jiancheng.
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2016-02-17 3:16 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-02-05 2:31 [RESEND PATCH v8 0/6] ARM: hisi: Add initial support including clock driver for Hi3519 soc Jiancheng Xue
2016-02-05 2:31 ` [RESEND PATCH v8 1/6] clk: hisilicon: add CRG driver for hi3519 soc Jiancheng Xue
2016-02-17 0:46 ` Michael Turquette
2016-02-17 3:08 ` xuejiancheng
2016-02-05 2:31 ` [RESEND PATCH v8 2/6] ARM: hisi: add compatible string for Hi3519 soc Jiancheng Xue
2016-02-05 2:31 ` [RESEND PATCH v8 3/6] ARM: config: hisi: enable CONFIG_RESET_CONTROLLER Jiancheng Xue
2016-02-05 2:31 ` [RESEND PATCH v8 4/6] ARM: debug: add hi3519 debug uart Jiancheng Xue
2016-02-05 2:31 ` [RESEND PATCH v8 5/6] ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl Jiancheng Xue
2016-02-05 2:31 ` [RESEND PATCH v8 6/6] ARM: dts: add dts files for Hi3519 Jiancheng Xue
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