From: Conor Dooley <conor@kernel.org>
To: Charlie Jenkins <charlie@rivosinc.com>
Cc: "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
"Palmer Dabbelt" <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v4 06/16] riscv: Introduce vendor variants of extension helpers
Date: Wed, 1 May 2024 12:29:56 +0100 [thread overview]
Message-ID: <20240501-tripping-acetone-e556e993ba95@spud> (raw)
In-Reply-To: <20240426-dev-charlie-support_thead_vector_6_9-v4-6-b692f3c516ec@rivosinc.com>
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On Fri, Apr 26, 2024 at 02:29:20PM -0700, Charlie Jenkins wrote:
> index c073494519eb..dd7e8e0c0af1 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -844,25 +844,41 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
> {
> struct alt_entry *alt;
> void *oldptr, *altptr;
> - u16 id, value;
> + u16 id, value, vendor;
>
> if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> return;
>
> for (alt = begin; alt < end; alt++) {
> - if (alt->vendor_id != 0)
> - continue;
> -
> id = PATCH_ID_CPUFEATURE_ID(alt->patch_id);
> + vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id);
>
> - if (id >= RISCV_ISA_EXT_MAX) {
> + /*
> + * Any alternative with a patch_id that is less than
> + * RISCV_ISA_EXT_MAX is interpreted as a standard extension.
> + *
> + * Any alternative with patch_id that is greater than or equal
> + * to RISCV_VENDOR_EXT_ALTERNATIVES_BASE is interpreted as a
> + * vendor extension.
I think this stuff is all fine, since we can always re-jig things in the
future if needs be.
> + */
> + if (id < RISCV_ISA_EXT_MAX) {
> + /*
> + * This patch should be treated as errata so skip
> + * processing here.
> + */
> + if (alt->vendor_id != 0)
> + continue;
> +
> + if (!__riscv_isa_extension_available(NULL, id))
> + continue;
> + } else if (id >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE) {
> + if (!__riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, id))
> + continue;
> + } else {
> WARN(1, "This extension id:%d is not in ISA extension list", id);
> continue;
> }
>
> - if (!__riscv_isa_extension_available(NULL, id))
> - continue;
> -
> value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id);
> if (!riscv_cpufeature_patch_check(id, value))
> continue;
> diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c
> index f76cb3013c2d..eced93eec5a6 100644
> --- a/arch/riscv/kernel/vendor_extensions.c
> +++ b/arch/riscv/kernel/vendor_extensions.c
> @@ -3,6 +3,7 @@
> * Copyright 2024 Rivos, Inc
> */
>
> +#include <asm/vendorid_list.h>
> #include <asm/vendor_extensions.h>
> #include <asm/vendor_extensions/thead.h>
>
> @@ -16,3 +17,42 @@ const struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[] = {
> };
>
> const size_t riscv_isa_vendor_ext_list_size = ARRAY_SIZE(riscv_isa_vendor_ext_list);
> +
> +/**
> + * __riscv_isa_vendor_extension_available() - Check whether given vendor
> + * extension is available or not.
> + *
> + * @cpu: check if extension is available on this cpu
> + * @vendor: vendor that the extension is a member of
> + * @bit: bit position of the desired extension
> + * Return: true or false
> + *
> + * NOTE: When cpu is -1, will check if extension is available on all cpus
> + */
> +bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsigned int bit)
> +{
> + unsigned long *bmap;
> + struct riscv_isainfo *cpu_bmap;
> + size_t bmap_size;
> +
> + switch (vendor) {
> +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD
> + case THEAD_VENDOR_ID:
> + bmap = riscv_isa_vendor_ext_list_thead.vendor_bitmap;
> + cpu_bmap = riscv_isa_vendor_ext_list_thead.per_hart_vendor_bitmap;
> + bmap_size = riscv_isa_vendor_ext_list_thead.bitmap_size;
> + break;
> +#endif
> + default:
> + return false;
> + }
> +
> + if (cpu != -1)
> + bmap = cpu_bmap[cpu].isa;
> +
> + if (bit >= bmap_size)
> + return false;
> +
> + return test_bit(bit, bmap) ? true : false;
> +}
> +EXPORT_SYMBOL_GPL(__riscv_isa_vendor_extension_available);
I wonder if we care to implement a non __ prefixed version of this, like
the standard stuff? The only __ version users of the standard one are in
kvm and core arch code, the "external" users all use the non-prefixed
version.
In any case,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
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next prev parent reply other threads:[~2024-05-01 11:30 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-26 21:29 [PATCH v4 00/16] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-04-26 21:29 ` [PATCH v4 01/16] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-04-26 21:29 ` [PATCH v4 02/16] dt-bindings: riscv: cpus: add a vlen register length property Charlie Jenkins
2024-04-26 21:29 ` [PATCH v4 03/16] riscv: vector: Use vlenb from DT Charlie Jenkins
2024-05-01 10:31 ` Conor Dooley
2024-05-01 16:46 ` Charlie Jenkins
2024-04-26 21:29 ` [PATCH v4 04/16] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-04-26 21:29 ` [PATCH v4 05/16] riscv: Extend cpufeature.c to detect vendor extensions Charlie Jenkins
2024-05-01 10:46 ` Conor Dooley
2024-05-01 17:04 ` Charlie Jenkins
2024-05-01 11:19 ` Conor Dooley
2024-05-01 17:06 ` Charlie Jenkins
2024-05-01 11:40 ` Conor Dooley
2024-05-01 17:10 ` Charlie Jenkins
2024-05-01 17:12 ` Conor Dooley
2024-05-01 16:44 ` Evan Green
2024-05-01 17:19 ` Conor Dooley
2024-05-01 17:58 ` Charlie Jenkins
2024-05-01 17:51 ` Charlie Jenkins
2024-05-01 18:03 ` Conor Dooley
2024-05-01 18:09 ` Conor Dooley
2024-05-01 18:37 ` Charlie Jenkins
2024-05-01 18:05 ` Evan Green
2024-05-02 22:31 ` Charlie Jenkins
2024-04-26 21:29 ` [PATCH v4 06/16] riscv: Introduce vendor variants of extension helpers Charlie Jenkins
2024-05-01 11:29 ` Conor Dooley [this message]
2024-05-01 19:45 ` Charlie Jenkins
2024-04-26 21:29 ` [PATCH v4 07/16] riscv: cpufeature: Extract common elements from extension checking Charlie Jenkins
2024-05-01 11:37 ` Conor Dooley
2024-05-01 19:48 ` Charlie Jenkins
2024-05-01 20:15 ` Conor Dooley
2024-05-01 20:39 ` Charlie Jenkins
2024-04-26 21:29 ` [PATCH v4 08/16] riscv: Convert xandespmu to use the vendor extension framework Charlie Jenkins
2024-05-01 11:38 ` Conor Dooley
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