From: "Inès Varhol" <ines.varhol@telecom-paris.fr>
To: qemu-devel@nongnu.org
Cc: "Laurent Vivier" <lvivier@redhat.com>,
"Thomas Huth" <thuth@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
qemu-arm@nongnu.org, "Alistair Francis" <alistair@alistair23.me>,
"Inès Varhol" <ines.varhol@telecom-paris.fr>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Arnaud Minier" <arnaud.minier@telecom-paris.fr>,
"Paolo Bonzini" <pbonzini@redhat.com>
Subject: [PATCH 1/4] hw/misc: Create STM32L4x5 SYSCFG clock
Date: Tue, 7 May 2024 20:55:38 +0200 [thread overview]
Message-ID: <20240507185854.34572-2-ines.varhol@telecom-paris.fr> (raw)
In-Reply-To: <20240507185854.34572-1-ines.varhol@telecom-paris.fr>
This commit creates a clock in STM32L4x5 SYSCFG and wires it up to the
corresponding clock from STM32L4x5 RCC.
A read-only QOM property allowing to read the clock frequency is added
(it will be used in a QTest).
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
---
Hello,
Several people noticed that replicating the code in the
different devices is a bad idea (cf cover letter).
One proposition is to directly add the clock property
in `qdev_init_clock_in()`.
Would that be acceptable and are there other alternatives
(allowing to the clock frequency from a Qtest)?
Best regards,
Inès Varhol
include/hw/misc/stm32l4x5_syscfg.h | 1 +
hw/arm/stm32l4x5_soc.c | 2 ++
hw/misc/stm32l4x5_syscfg.c | 30 ++++++++++++++++++++++++++++--
3 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/include/hw/misc/stm32l4x5_syscfg.h b/include/hw/misc/stm32l4x5_syscfg.h
index 23bb564150..c450df2b9e 100644
--- a/include/hw/misc/stm32l4x5_syscfg.h
+++ b/include/hw/misc/stm32l4x5_syscfg.h
@@ -48,6 +48,7 @@ struct Stm32l4x5SyscfgState {
uint32_t swpr2;
qemu_irq gpio_out[GPIO_NUM_PINS];
+ Clock *clk;
};
#endif
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
index 38f7a2d5d9..fb2afa6cfe 100644
--- a/hw/arm/stm32l4x5_soc.c
+++ b/hw/arm/stm32l4x5_soc.c
@@ -236,6 +236,8 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
/* System configuration controller */
busdev = SYS_BUS_DEVICE(&s->syscfg);
+ qdev_connect_clock_in(DEVICE(&s->syscfg), "clk",
+ qdev_get_clock_out(DEVICE(&(s->rcc)), "syscfg-out"));
if (!sysbus_realize(busdev, errp)) {
return;
}
diff --git a/hw/misc/stm32l4x5_syscfg.c b/hw/misc/stm32l4x5_syscfg.c
index a5a1ce2680..7e6125383e 100644
--- a/hw/misc/stm32l4x5_syscfg.c
+++ b/hw/misc/stm32l4x5_syscfg.c
@@ -26,6 +26,10 @@
#include "trace.h"
#include "hw/irq.h"
#include "migration/vmstate.h"
+#include "hw/clock.h"
+#include "hw/qdev-clock.h"
+#include "qapi/visitor.h"
+#include "qapi/error.h"
#include "hw/misc/stm32l4x5_syscfg.h"
#include "hw/gpio/stm32l4x5_gpio.h"
@@ -202,6 +206,14 @@ static void stm32l4x5_syscfg_write(void *opaque, hwaddr addr,
}
}
+static void clock_freq_get(Object *obj, Visitor *v,
+ const char *name, void *opaque, Error **errp)
+{
+ Stm32l4x5SyscfgState *s = STM32L4X5_SYSCFG(obj);
+ uint32_t clock_freq_hz = clock_get_hz(s->clk);
+ visit_type_uint32(v, name, &clock_freq_hz, errp);
+}
+
static const MemoryRegionOps stm32l4x5_syscfg_ops = {
.read = stm32l4x5_syscfg_read,
.write = stm32l4x5_syscfg_write,
@@ -225,12 +237,24 @@ static void stm32l4x5_syscfg_init(Object *obj)
qdev_init_gpio_in(DEVICE(obj), stm32l4x5_syscfg_set_irq,
GPIO_NUM_PINS * NUM_GPIOS);
qdev_init_gpio_out(DEVICE(obj), s->gpio_out, GPIO_NUM_PINS);
+ s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0);
+ object_property_add(obj, "clock-freq-hz", "uint32", clock_freq_get, NULL,
+ NULL, NULL);
+}
+
+static void stm32l4x5_syscfg_realize(DeviceState *dev, Error **errp)
+{
+ Stm32l4x5SyscfgState *s = STM32L4X5_SYSCFG(dev);
+ if (!clock_has_source(s->clk)) {
+ error_setg(errp, "SYSCFG: clk input must be connected");
+ return;
+ }
}
static const VMStateDescription vmstate_stm32l4x5_syscfg = {
.name = TYPE_STM32L4X5_SYSCFG,
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_UINT32(memrmp, Stm32l4x5SyscfgState),
VMSTATE_UINT32(cfgr1, Stm32l4x5SyscfgState),
@@ -241,6 +265,7 @@ static const VMStateDescription vmstate_stm32l4x5_syscfg = {
VMSTATE_UINT32(swpr, Stm32l4x5SyscfgState),
VMSTATE_UINT32(skr, Stm32l4x5SyscfgState),
VMSTATE_UINT32(swpr2, Stm32l4x5SyscfgState),
+ VMSTATE_CLOCK(clk, Stm32l4x5SyscfgState),
VMSTATE_END_OF_LIST()
}
};
@@ -251,6 +276,7 @@ static void stm32l4x5_syscfg_class_init(ObjectClass *klass, void *data)
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->vmsd = &vmstate_stm32l4x5_syscfg;
+ dc->realize = stm32l4x5_syscfg_realize;
rc->phases.hold = stm32l4x5_syscfg_hold_reset;
}
--
2.43.2
next prev parent reply other threads:[~2024-05-07 19:00 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-07 18:55 [PATCH 0/4] Check clock connection between STM32L4x5 RCC and peripherals Inès Varhol
2024-05-07 18:55 ` Inès Varhol [this message]
2024-05-07 18:55 ` [PATCH 2/4] hw/gpio: Handle clock migration in STM32L4x5 gpios Inès Varhol
2024-05-08 8:26 ` Philippe Mathieu-Daudé
2024-05-07 18:55 ` [PATCH 3/4] hw/char: Add QOM property for STM32L4x5 USART clock frequency Inès Varhol
2024-05-07 18:55 ` [PATCH 4/4] tests/qtest: Check STM32L4x5 clock connections Inès Varhol
2024-05-20 14:36 ` [PATCH 0/4] Check clock connection between STM32L4x5 RCC and peripherals Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2024-05-05 14:05 Inès Varhol
2024-05-05 14:05 ` [PATCH 1/4] hw/misc: Create STM32L4x5 SYSCFG clock Inès Varhol
2024-05-07 9:50 ` Peter Maydell
2024-05-07 17:30 ` Inès Varhol
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