From: "Fea.Wang" <fea.wang@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Jim Shu <jim.shu@sifive.com>, "Fea . Wang" <fea.wang@sifive.com>,
Frank Chang <frank.chang@sifive.com>,
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Max Chou <max.chou@sifive.com>
Subject: [RESEND PATCH v2 1/5] target/riscv: Reuse the conversion function of priv_spec
Date: Wed, 15 May 2024 16:05:58 +0800 [thread overview]
Message-ID: <20240515080605.2675399-2-fea.wang@sifive.com> (raw)
In-Reply-To: <20240515080605.2675399-1-fea.wang@sifive.com>
From: Jim Shu <jim.shu@sifive.com>
Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c
could also use it.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 1 +
target/riscv/tcg/tcg-cpu.c | 13 ++++---------
3 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2946ac298a..6dd3d7f4a3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1786,7 +1786,7 @@ static int priv_spec_from_str(const char *priv_spec_str)
return priv_version;
}
-static const char *priv_spec_to_str(int priv_version)
+const char *priv_spec_to_str(int priv_version)
{
switch (priv_version) {
case PRIV_VERSION_1_10_0:
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1501868008..140eb43fcb 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -833,4 +833,5 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
/* Implemented in th_csr.c */
void th_register_custom_csrs(RISCVCPU *cpu);
+const char *priv_spec_to_str(int priv_version);
#endif /* RISCV_CPU_H */
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index f59b5d7f2d..fa186093fb 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -76,16 +76,11 @@ static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit,
static const char *cpu_priv_ver_to_str(int priv_ver)
{
- switch (priv_ver) {
- case PRIV_VERSION_1_10_0:
- return "v1.10.0";
- case PRIV_VERSION_1_11_0:
- return "v1.11.0";
- case PRIV_VERSION_1_12_0:
- return "v1.12.0";
- }
+ const char *priv_spec_str = priv_spec_to_str(priv_ver);
- g_assert_not_reached();
+ g_assert(priv_spec_str);
+
+ return priv_spec_str;
}
static void riscv_cpu_synchronize_from_tb(CPUState *cs,
--
2.34.1
next prev parent reply other threads:[~2024-05-15 8:02 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-15 8:05 [RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec Fea.Wang
2024-05-15 8:05 ` Fea.Wang [this message]
2024-05-15 8:05 ` [RESEND PATCH v2 2/5] target/riscv: Support the version for ss1p13 Fea.Wang
2024-05-15 8:06 ` [RESEND PATCH v2 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0 Fea.Wang
2024-05-21 6:49 ` LIU Zhiwei
2024-05-15 8:06 ` [RESEND PATCH v2 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 Fea.Wang
2024-05-15 8:06 ` [RESEND PATCH v2 5/5] target/riscv: Reserve exception codes for sw-check and hw-err Fea.Wang
2024-05-27 9:21 ` [RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec Daniel Henrique Barboza
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