From: "Fea.Wang" <fea.wang@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: "Fea.Wang" <fea.wang@sifive.com>,
Frank Chang <frank.chang@sifive.com>,
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [RESEND PATCH v2 5/5] target/riscv: Reserve exception codes for sw-check and hw-err
Date: Wed, 15 May 2024 16:06:02 +0800 [thread overview]
Message-ID: <20240515080605.2675399-6-fea.wang@sifive.com> (raw)
In-Reply-To: <20240515080605.2675399-1-fea.wang@sifive.com>
Based on the priv-1.13.0, add the exception codes for Software-check and
Hardware-error.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu_bits.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index f888025c59..f037f727d9 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -673,6 +673,8 @@ typedef enum RISCVException {
RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
+ RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */
+ RISCV_EXCP_HW_ERR = 0x13, /* since: priv-1.13.0 */
RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
--
2.34.1
next prev parent reply other threads:[~2024-05-15 8:02 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-15 8:05 [RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec Fea.Wang
2024-05-15 8:05 ` [RESEND PATCH v2 1/5] target/riscv: Reuse the conversion function of priv_spec Fea.Wang
2024-05-15 8:05 ` [RESEND PATCH v2 2/5] target/riscv: Support the version for ss1p13 Fea.Wang
2024-05-15 8:06 ` [RESEND PATCH v2 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0 Fea.Wang
2024-05-21 6:49 ` LIU Zhiwei
2024-05-15 8:06 ` [RESEND PATCH v2 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 Fea.Wang
2024-05-15 8:06 ` Fea.Wang [this message]
2024-05-27 9:21 ` [RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec Daniel Henrique Barboza
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