From: Alistair Francis <alistair23@gmail.com>
To: Irina Ryapolova <irina.ryapolova@syntacore.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com,
Vadim Shakirov <vadim.shakirov@syntacore.com>
Subject: Re: [PATCH 2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS
Date: Thu, 15 Feb 2024 19:46:50 +1000 [thread overview]
Message-ID: <CAKmqyKMXuykxif+ezzVkxjFA6m5vECj9088GjFPiyRvCQqtT0Q@mail.gmail.com> (raw)
In-Reply-To: <20240212171156.47293-2-irina.ryapolova@syntacore.com>
On Tue, Feb 13, 2024 at 3:13 AM Irina Ryapolova
<irina.ryapolova@syntacore.com> wrote:
>
> From: Vadim Shakirov <vadim.shakirov@syntacore.com>
>
> In the AIA specification in the paragraph "Virtual interrupts for VS level"
> it is indicated for interrupts 13-63: if the bit in hideleg is enabled,
> then the corresponding vsip and vsie bits are aliases to sip and sie
@Atish Patra in case you know something I don't
>
> Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 0c21145eaf..51b1099e10 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1136,7 +1136,7 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
> static const uint64_t delegable_ints =
> S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP;
> static const uint64_t vs_delegable_ints =
> - (VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & ~MIP_LCOFIP;
> + VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS;
> static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
> HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS;
> #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2024-02-15 9:47 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-12 17:11 [PATCH 1/2] target/riscv/csr.c: Add functional of hvictl CSR Irina Ryapolova
2024-02-12 17:11 ` [PATCH 2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS Irina Ryapolova
2024-02-15 9:46 ` Alistair Francis [this message]
2024-02-15 9:42 ` [PATCH 1/2] target/riscv/csr.c: Add functional of hvictl CSR Alistair Francis
-- strict thread matches above, loose matches on Subject: below --
2024-02-12 17:13 Irina Ryapolova
2024-02-12 17:13 ` [PATCH 2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS Irina Ryapolova
2023-12-21 11:36 [PATCH 0/2] " Vadim Shakirov
2023-12-21 11:36 ` [PATCH 2/2] target/riscv/csr: " Vadim Shakirov
2023-12-21 16:03 ` Daniel Henrique Barboza
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