From: Sunil V L <sunilvl@ventanamicro.com>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: X512 <danger_mail@list.ru>,
qemu-devel@nongnu.org, qemu-riscv <qemu-riscv@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PATCH] target/riscv: fix ACPI MCFG table
Date: Tue, 20 Feb 2024 10:58:22 +0530 [thread overview]
Message-ID: <ZdQ4dlMovqdrN+kz@sunil-laptop> (raw)
In-Reply-To: <6960207f-eaaa-4cfd-a4e3-3118da697ef7@linaro.org>
On Mon, Feb 19, 2024 at 05:43:56PM +0100, Philippe Mathieu-Daudé wrote:
> On 19/2/24 17:09, X512 via wrote:
> > MCFG segments should point to PCI configuration range, not BAR MMIO.
> >
>
> Fixes: 55ecd83b36 ("hw/riscv/virt-acpi-build.c: Add IO controllers and
> devices")
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>
> > Signed-off-by: Ilya Chugin <danger_mail@list.ru>
> > ---
> > hw/riscv/virt-acpi-build.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> > index fb8baf64f6..fe01b626ea 100644
> > --- a/hw/riscv/virt-acpi-build.c
> > +++ b/hw/riscv/virt-acpi-build.c
> > @@ -558,8 +558,8 @@ static void virt_acpi_build(RISCVVirtState *s,
> > AcpiBuildTables *tables)
> > acpi_add_table(table_offsets, tables_blob);
> > {
> > AcpiMcfgInfo mcfg = {
> > - .base = s->memmap[VIRT_PCIE_MMIO].base,
> > - .size = s->memmap[VIRT_PCIE_MMIO].size,
> > + .base = s->memmap[VIRT_PCIE_ECAM].base,
> > + .size = s->memmap[VIRT_PCIE_ECAM].size,
Thanks!.
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
> > };
> > build_mcfg(tables_blob, tables->linker, &mcfg, s->oem_id,
> > s->oem_table_id);
>
prev parent reply other threads:[~2024-02-20 5:28 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <180d236d-c8e4-411a-b4d2-632eb82092fa@list.ru>
2024-02-19 16:43 ` [PATCH] target/riscv: fix ACPI MCFG table Philippe Mathieu-Daudé
2024-02-20 5:28 ` Sunil V L [this message]
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