From: Alexander Stein <alexanders83@web.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/5] arm1176/cpu: Add icache and dcache support
Date: Sat, 4 Jul 2015 11:48:41 +0200 [thread overview]
Message-ID: <1436003324-8769-3-git-send-email-alexanders83@web.de> (raw)
In-Reply-To: <1436003324-8769-1-git-send-email-alexanders83@web.de>
The code is copied 1:1 from arm1136 which uses the same cp15 registers.
Signed-off-by: Alexander Stein <alexanders83@web.de>
---
arch/arm/cpu/arm1176/cpu.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 97 insertions(+)
diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c
index 24b5cc7..2ff0e25 100644
--- a/arch/arm/cpu/arm1176/cpu.c
+++ b/arch/arm/cpu/arm1176/cpu.c
@@ -51,3 +51,100 @@ static void cache_flush(void)
/* mem barrier to sync things */
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#endif
+
+void invalidate_dcache_all(void)
+{
+ asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+}
+
+void flush_dcache_all(void)
+{
+ asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
+ asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+static int check_cache_range(unsigned long start, unsigned long stop)
+{
+ int ok = 1;
+
+ if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+ ok = 0;
+
+ if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+ ok = 0;
+
+ if (!ok)
+ debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+ start, stop);
+
+ return ok;
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ if (!check_cache_range(start, stop))
+ return;
+
+ while (start < stop) {
+ asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
+ start += CONFIG_SYS_CACHELINE_SIZE;
+ }
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ if (!check_cache_range(start, stop))
+ return;
+
+ while (start < stop) {
+ asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
+ start += CONFIG_SYS_CACHELINE_SIZE;
+ }
+
+ asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+ flush_dcache_range(start, start + size);
+}
+
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
+#endif
--
2.4.5
next prev parent reply other threads:[~2015-07-04 9:48 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-04 9:48 [U-Boot] [PATCH 0/5] dcache support for Raspberry Pi 1 Alexander Stein
2015-07-04 9:48 ` [U-Boot] [PATCH 1/5] arm1176/cpu: Match cache_flush to arm1136 Alexander Stein
2015-07-11 5:20 ` Stephen Warren
2015-07-12 7:23 ` Alexander Stein
2015-07-04 9:48 ` Alexander Stein [this message]
2015-07-11 5:21 ` [U-Boot] [PATCH 2/5] arm1176/cpu: Add icache and dcache support Stephen Warren
2015-07-12 7:26 ` Alexander Stein
2015-07-14 4:57 ` Stephen Warren
2015-07-04 9:48 ` [U-Boot] [PATCH 3/5] arm1176/cpu: Align cache flushing addresses to cacheline size Alexander Stein
2015-07-11 5:21 ` Stephen Warren
2015-07-04 9:48 ` [U-Boot] [PATCH 4/5] arm/mach-bcm283x/mbox: Flush and invalidate dcache when using fw mailbox Alexander Stein
2015-07-11 5:24 ` Stephen Warren
2015-07-04 9:48 ` [U-Boot] [PATCH 5/5] arm/rpi: Enable dcache Alexander Stein
2015-07-11 5:24 ` Stephen Warren
2015-07-12 7:30 ` Alexander Stein
2015-07-14 4:57 ` Stephen Warren
2015-07-06 7:39 ` [U-Boot] [PATCH 0/5] dcache support for Raspberry Pi 1 Albert ARIBAUD
2015-07-06 18:24 ` Alexander Stein
2015-07-06 21:26 ` Albert ARIBAUD
2015-07-08 18:15 ` Alexander Stein
2015-07-08 22:47 ` Albert ARIBAUD
2015-07-11 5:17 ` Stephen Warren
2015-07-12 8:10 ` Alexander Stein
2015-07-14 5:02 ` Stephen Warren
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