All the mail mirrored from lore.kernel.org
 help / color / mirror / Atom feed
From: Alexander Stein <alexanders83@web.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 0/5] dcache support for Raspberry Pi 1
Date: Sat,  4 Jul 2015 11:48:39 +0200	[thread overview]
Message-ID: <1436003324-8769-1-git-send-email-alexanders83@web.de> (raw)

This patchset enables dcache support for Raspberry Pi 1.
First the cache support code was made similar to existing arm1136 code.
The invalidate and flush functions were inprovoed to accept also non-cacheline
aligned addresses. This reduces the cacheline size knowledge from generic
code.
Then rpi mailbox code has now dcache flush for writing the mailbox request and
a dcache invalidation for receiving the mailbox answer.
Finally the CONFIG_SYS_DCACHE_OFF switch got removed from rpi config.

dcache supprt increases the MMC read performance on RPI 1 from 5,4 MiB/s to
12.3 MiB/s. It doesn't seem to have any affect on RPI 2 though. I just get
error messages about non-cacheline aligned address upon invalidation.
The performance stucks at 1.2 MiB/s.

This was tested by the following command:
> fatload mmc 0:1 ${kernel_addr_r} zImage

Alexander Stein (5):
  arm1176/cpu: Match cache_flush to arm1136
  arm1176/cpu: Add icache and dcache support
  arm1176/cpu: Align cache flushing addresses to cacheline size
  arm/mach-bcm283x/mbox: Flush and invalidate dcache when using fw
    mailbox
  arm/rpi: Enable dcache

 arch/arm/cpu/arm1176/cpu.c   | 114 +++++++++++++++++++++++++++++++++++++++++--
 arch/arm/mach-bcm283x/mbox.c |   6 +++
 include/configs/rpi-common.h |   1 -
 3 files changed, 116 insertions(+), 5 deletions(-)

-- 
2.4.5

             reply	other threads:[~2015-07-04  9:48 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-04  9:48 Alexander Stein [this message]
2015-07-04  9:48 ` [U-Boot] [PATCH 1/5] arm1176/cpu: Match cache_flush to arm1136 Alexander Stein
2015-07-11  5:20   ` Stephen Warren
2015-07-12  7:23     ` Alexander Stein
2015-07-04  9:48 ` [U-Boot] [PATCH 2/5] arm1176/cpu: Add icache and dcache support Alexander Stein
2015-07-11  5:21   ` Stephen Warren
2015-07-12  7:26     ` Alexander Stein
2015-07-14  4:57       ` Stephen Warren
2015-07-04  9:48 ` [U-Boot] [PATCH 3/5] arm1176/cpu: Align cache flushing addresses to cacheline size Alexander Stein
2015-07-11  5:21   ` Stephen Warren
2015-07-04  9:48 ` [U-Boot] [PATCH 4/5] arm/mach-bcm283x/mbox: Flush and invalidate dcache when using fw mailbox Alexander Stein
2015-07-11  5:24   ` Stephen Warren
2015-07-04  9:48 ` [U-Boot] [PATCH 5/5] arm/rpi: Enable dcache Alexander Stein
2015-07-11  5:24   ` Stephen Warren
2015-07-12  7:30     ` Alexander Stein
2015-07-14  4:57       ` Stephen Warren
2015-07-06  7:39 ` [U-Boot] [PATCH 0/5] dcache support for Raspberry Pi 1 Albert ARIBAUD
2015-07-06 18:24   ` Alexander Stein
2015-07-06 21:26     ` Albert ARIBAUD
2015-07-08 18:15       ` Alexander Stein
2015-07-08 22:47         ` Albert ARIBAUD
2015-07-11  5:17 ` Stephen Warren
2015-07-12  8:10   ` Alexander Stein
2015-07-14  5:02     ` Stephen Warren

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1436003324-8769-1-git-send-email-alexanders83@web.de \
    --to=alexanders83@web.de \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.