From: Alexander Stein <alexanders83@web.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 3/5] arm1176/cpu: Align cache flushing addresses to cacheline size
Date: Sat, 4 Jul 2015 11:48:42 +0200 [thread overview]
Message-ID: <1436003324-8769-4-git-send-email-alexanders83@web.de> (raw)
In-Reply-To: <1436003324-8769-1-git-send-email-alexanders83@web.de>
cache flushing addresses must be cacheline size aligned, so mask the
start and stop address appropriately.
Signed-off-by: Alexander Stein <alexanders83@web.de>
---
arch/arm/cpu/arm1176/cpu.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c
index 2ff0e25..5ac8e79 100644
--- a/arch/arm/cpu/arm1176/cpu.c
+++ b/arch/arm/cpu/arm1176/cpu.c
@@ -57,6 +57,7 @@ static void cache_flush(void)
#ifndef CONFIG_SYS_CACHELINE_SIZE
#define CONFIG_SYS_CACHELINE_SIZE 32
#endif
+#define CACHLINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1)
void invalidate_dcache_all(void)
{
@@ -88,6 +89,9 @@ static int check_cache_range(unsigned long start, unsigned long stop)
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
+ stop = (stop + CACHLINE_MASK) & ~CACHLINE_MASK;
+ start &= ~CACHLINE_MASK;
+
if (!check_cache_range(start, stop))
return;
@@ -99,6 +103,9 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop)
void flush_dcache_range(unsigned long start, unsigned long stop)
{
+ stop = (stop + CACHLINE_MASK) & ~CACHLINE_MASK;
+ start &= ~CACHLINE_MASK;
+
if (!check_cache_range(start, stop))
return;
--
2.4.5
next prev parent reply other threads:[~2015-07-04 9:48 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-04 9:48 [U-Boot] [PATCH 0/5] dcache support for Raspberry Pi 1 Alexander Stein
2015-07-04 9:48 ` [U-Boot] [PATCH 1/5] arm1176/cpu: Match cache_flush to arm1136 Alexander Stein
2015-07-11 5:20 ` Stephen Warren
2015-07-12 7:23 ` Alexander Stein
2015-07-04 9:48 ` [U-Boot] [PATCH 2/5] arm1176/cpu: Add icache and dcache support Alexander Stein
2015-07-11 5:21 ` Stephen Warren
2015-07-12 7:26 ` Alexander Stein
2015-07-14 4:57 ` Stephen Warren
2015-07-04 9:48 ` Alexander Stein [this message]
2015-07-11 5:21 ` [U-Boot] [PATCH 3/5] arm1176/cpu: Align cache flushing addresses to cacheline size Stephen Warren
2015-07-04 9:48 ` [U-Boot] [PATCH 4/5] arm/mach-bcm283x/mbox: Flush and invalidate dcache when using fw mailbox Alexander Stein
2015-07-11 5:24 ` Stephen Warren
2015-07-04 9:48 ` [U-Boot] [PATCH 5/5] arm/rpi: Enable dcache Alexander Stein
2015-07-11 5:24 ` Stephen Warren
2015-07-12 7:30 ` Alexander Stein
2015-07-14 4:57 ` Stephen Warren
2015-07-06 7:39 ` [U-Boot] [PATCH 0/5] dcache support for Raspberry Pi 1 Albert ARIBAUD
2015-07-06 18:24 ` Alexander Stein
2015-07-06 21:26 ` Albert ARIBAUD
2015-07-08 18:15 ` Alexander Stein
2015-07-08 22:47 ` Albert ARIBAUD
2015-07-11 5:17 ` Stephen Warren
2015-07-12 8:10 ` Alexander Stein
2015-07-14 5:02 ` Stephen Warren
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