From: Stafford Horne <shorne@gmail.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Jonas Bonn <jonas@southpole.se>,
"David S. Miller" <davem@davemloft.net>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Randy Dunlap <rdunlap@infradead.org>,
devicetree@vger.kernel.org, openrisc@lists.librecores.org
Subject: Re: [PATCH v4 05/13] irqchip: add initial support for ompic
Date: Mon, 30 Oct 2017 13:18:06 +0900 [thread overview]
Message-ID: <20171030041806.GA29237@lianli.shorne-pla.net> (raw)
In-Reply-To: <86mv4974ht.fsf@arm.com>
On Mon, Oct 30, 2017 at 02:29:18AM +0000, Marc Zyngier wrote:
> On Mon, Oct 30 2017 at 8:11:15 am GMT, Stafford Horne <shorne@gmail.com> wrote:
> > From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> >
> > IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
> > described in the Multi-core support section of the OpenRISC 1.2
> > architecture specification:
> >
> > https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf
> >
> > Each OpenRISC core contains a full interrupt controller which is used in
> > the SMP architecture for interrupt balancing. This IPI device, the
> > ompic, is the only external device required for enabling SMP on
> > OpenRISC.
> >
> > Pending ops are stored in a memory bit mask which can allow multiple
> > pending operations to be set and serviced at a time. This is mostly
> > borrowed from the alpha IPI implementation.
> >
> > Cc: Marc Zyngier <marc.zyngier@arm.com>
> > Acked-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> > [shorne@gmail.com: converted ops to bitmask, wrote commit message]
> > Signed-off-by: Stafford Horne <shorne@gmail.com>
>
> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Thanks
> Side question: what is your merge strategy for this? I can take it
> through the irqchip tree as it is standalone, but I'm open to other
> suggestions.
For me its easier if I just take it through the openrisc tree, as
there are dependencies between this series and the irqchip driver.
If you are ok with that I can make a note to Linus indicating so in
the pull request.
My plan is to send this series during the 4.15 merge window.
-Stafford
WARNING: multiple messages have this Message-ID (diff)
From: Stafford Horne <shorne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
Cc: LKML <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
Stefan Kristiansson
<stefan.kristiansson-MbMCFXIvDHJFcC0YU169RA@public.gmane.org>,
Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>,
Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Jonas Bonn <jonas-A9uVI2HLR7kOP4wsBPIw7w@public.gmane.org>,
"David S. Miller" <davem-fT/PcQaiUtIeIZ0/mPfg9Q@public.gmane.org>,
Greg Kroah-Hartman
<gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>,
Mauro Carvalho Chehab
<mchehab-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Randy Dunlap <rdunlap-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
openrisc-cunTk1MwBs9a3B2Vnqf2dGD2FQJk+8+b@public.gmane.org
Subject: Re: [PATCH v4 05/13] irqchip: add initial support for ompic
Date: Mon, 30 Oct 2017 13:18:06 +0900 [thread overview]
Message-ID: <20171030041806.GA29237@lianli.shorne-pla.net> (raw)
In-Reply-To: <86mv4974ht.fsf-5wv7dgnIgG8@public.gmane.org>
On Mon, Oct 30, 2017 at 02:29:18AM +0000, Marc Zyngier wrote:
> On Mon, Oct 30 2017 at 8:11:15 am GMT, Stafford Horne <shorne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> > From: Stefan Kristiansson <stefan.kristiansson-MbMCFXIvDHJFcC0YU169RA@public.gmane.org>
> >
> > IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
> > described in the Multi-core support section of the OpenRISC 1.2
> > architecture specification:
> >
> > https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf
> >
> > Each OpenRISC core contains a full interrupt controller which is used in
> > the SMP architecture for interrupt balancing. This IPI device, the
> > ompic, is the only external device required for enabling SMP on
> > OpenRISC.
> >
> > Pending ops are stored in a memory bit mask which can allow multiple
> > pending operations to be set and serviced at a time. This is mostly
> > borrowed from the alpha IPI implementation.
> >
> > Cc: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
> > Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> > Signed-off-by: Stefan Kristiansson <stefan.kristiansson-MbMCFXIvDHJFcC0YU169RA@public.gmane.org>
> > [shorne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org: converted ops to bitmask, wrote commit message]
> > Signed-off-by: Stafford Horne <shorne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> Reviewed-by: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
Thanks
> Side question: what is your merge strategy for this? I can take it
> through the irqchip tree as it is standalone, but I'm open to other
> suggestions.
For me its easier if I just take it through the openrisc tree, as
there are dependencies between this series and the irqchip driver.
If you are ok with that I can make a note to Linus indicating so in
the pull request.
My plan is to send this series during the 4.15 merge window.
-Stafford
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WARNING: multiple messages have this Message-ID (diff)
From: Stafford Horne <shorne@gmail.com>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH v4 05/13] irqchip: add initial support for ompic
Date: Mon, 30 Oct 2017 13:18:06 +0900 [thread overview]
Message-ID: <20171030041806.GA29237@lianli.shorne-pla.net> (raw)
In-Reply-To: <86mv4974ht.fsf@arm.com>
On Mon, Oct 30, 2017 at 02:29:18AM +0000, Marc Zyngier wrote:
> On Mon, Oct 30 2017 at 8:11:15 am GMT, Stafford Horne <shorne@gmail.com> wrote:
> > From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> >
> > IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
> > described in the Multi-core support section of the OpenRISC 1.2
> > architecture specification:
> >
> > https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf
> >
> > Each OpenRISC core contains a full interrupt controller which is used in
> > the SMP architecture for interrupt balancing. This IPI device, the
> > ompic, is the only external device required for enabling SMP on
> > OpenRISC.
> >
> > Pending ops are stored in a memory bit mask which can allow multiple
> > pending operations to be set and serviced at a time. This is mostly
> > borrowed from the alpha IPI implementation.
> >
> > Cc: Marc Zyngier <marc.zyngier@arm.com>
> > Acked-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> > [shorne at gmail.com: converted ops to bitmask, wrote commit message]
> > Signed-off-by: Stafford Horne <shorne@gmail.com>
>
> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Thanks
> Side question: what is your merge strategy for this? I can take it
> through the irqchip tree as it is standalone, but I'm open to other
> suggestions.
For me its easier if I just take it through the openrisc tree, as
there are dependencies between this series and the irqchip driver.
If you are ok with that I can make a note to Linus indicating so in
the pull request.
My plan is to send this series during the 4.15 merge window.
-Stafford
next prev parent reply other threads:[~2017-10-30 4:18 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-29 23:11 [PATCH v4 00/13] OpenRISC SMP Support Stafford Horne
2017-10-29 23:11 ` [PATCH v4 01/13] openrisc: use shadow registers to save regs on exception Stafford Horne
2017-10-29 23:11 ` [OpenRISC] " Stafford Horne
2017-10-29 23:11 ` [PATCH v4 02/13] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne
2017-10-29 23:11 ` [OpenRISC] " Stafford Horne
2017-10-29 23:11 ` [PATCH v4 03/13] openrisc: use qspinlocks and qrwlocks Stafford Horne
2017-10-29 23:11 ` [OpenRISC] " Stafford Horne
2017-10-29 23:11 ` [PATCH v4 04/13] dt-bindings: add openrisc to vendor prefixes list Stafford Horne
2017-10-29 23:11 ` [PATCH v4 05/13] irqchip: add initial support for ompic Stafford Horne
2017-10-29 23:11 ` [OpenRISC] " Stafford Horne
2017-10-30 2:29 ` Marc Zyngier
2017-10-30 2:29 ` [OpenRISC] " Marc Zyngier
2017-10-30 2:29 ` Marc Zyngier
2017-10-30 4:18 ` Stafford Horne [this message]
2017-10-30 4:18 ` [OpenRISC] " Stafford Horne
2017-10-30 4:18 ` Stafford Horne
2017-10-30 6:11 ` Marc Zyngier
2017-10-30 6:11 ` [OpenRISC] " Marc Zyngier
2017-11-01 12:17 ` Stafford Horne
2017-11-01 12:17 ` [OpenRISC] " Stafford Horne
2017-11-01 12:17 ` Stafford Horne
2017-10-29 23:11 ` [PATCH v4 06/13] openrisc: initial SMP support Stafford Horne
2017-10-29 23:11 ` [OpenRISC] " Stafford Horne
2017-10-29 23:11 ` [PATCH v4 07/13] openrisc: fix initial preempt state for secondary cpu tasks Stafford Horne
2017-10-29 23:11 ` [OpenRISC] " Stafford Horne
2017-10-29 23:11 ` [PATCH v4 08/13] openrisc: sleep instead of spin on secondary wait Stafford Horne
2017-10-29 23:11 ` [OpenRISC] " Stafford Horne
2017-10-29 23:11 ` [PATCH v4 09/13] openrisc: add cacheflush support to fix icache aliasing Stafford Horne
2017-10-29 23:11 ` [OpenRISC] " Stafford Horne
2017-10-29 23:11 ` [PATCH v4 10/13] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne
2017-10-29 23:11 ` [OpenRISC] " Stafford Horne
2017-10-29 23:11 ` [PATCH v4 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT Stafford Horne
2017-10-29 23:11 ` [OpenRISC] " Stafford Horne
2017-10-29 23:11 ` [PATCH v4 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing Stafford Horne
2017-10-29 23:11 ` [OpenRISC] " Stafford Horne
2017-10-29 23:11 ` [PATCH v4 13/13] openrisc: add tick timer multi-core sync logic Stafford Horne
2017-10-29 23:11 ` [OpenRISC] " Stafford Horne
2017-10-31 14:06 ` Matt Redfearn
2017-10-31 14:06 ` [OpenRISC] " Matt Redfearn
2017-10-31 23:17 ` Stafford Horne
2017-10-31 23:17 ` [OpenRISC] " Stafford Horne
2017-11-01 0:34 ` Stafford Horne
2017-11-01 0:34 ` [OpenRISC] " Stafford Horne
2017-11-01 9:26 ` Matt Redfearn
2017-11-01 9:26 ` [OpenRISC] " Matt Redfearn
2017-11-01 9:26 ` Matt Redfearn
2017-11-01 12:15 ` Stafford Horne
2017-11-01 12:15 ` [OpenRISC] " Stafford Horne
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