From: Stephen Warren <swarren@wwwdotorg.org>
To: Eric Anholt <eric@anholt.net>, linux-arm-kernel@lists.infradead.org
Cc: linux-rpi-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Lee Jones <lee@kernel.org>,
devicetree@vger.kernel.org, Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Andrea Merello <andrea.merello@gmail.com>
Subject: Re: [PATCH 4/4] irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2.
Date: Fri, 10 Jul 2015 23:13:15 -0600 [thread overview]
Message-ID: <55A0A5EB.4090007@wwwdotorg.org> (raw)
In-Reply-To: <1436303617-17185-5-git-send-email-eric@anholt.net>
On 07/07/2015 03:13 PM, Eric Anholt wrote:
> This interrupt controller is the new root interrupt controller with
> the timer, PMU events, and IPIs, and the bcm2835's interrupt
> controller is chained off of it to handle the peripherals.
>
> SMP IPI support was mostly written by Andrea Merello, while I wrote
> most of the rest of the IRQ handling.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Eric Anholt <eric@anholt.net>
I'd expect the git patch author to be Andrea if he wrote the original
patch and you enhanced it.
> diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c
> +struct arm_local_intc {
> + struct irq_domain *domain;
> + void __iomem *base;
> +};
> +
> +static struct arm_local_intc intc __read_mostly;
It'd be nice to give everything (types, functions, variables) a
consistent symbol prefix; bcm2836_arm_irqchip_ sounds like a good
bikeshed to me, but perhaps just propagating the above arm_local_ to the
functions too would be good, although that seems to risk symbol name
collisions with other ARM SoCs.
> +static void bcm2836_mask_per_cpu_irq(unsigned int reg, unsigned int bit)
> +{
> + void __iomem *reg_base = intc.base + reg;
> + unsigned int i;
> +
> + for (i = 0; i < 4; i++)
Is "4" there the CPU count? Perhaps this should use one of the Linux
APIs to query the CPU count rather than hard-coding it?
Should per-CPU IRQs automatically be masked on all CPUs at once, or only
on the current CPU? A very quick look at the ARM GIC driver implies it
doesn't iterate over all CPUs when masking per-CPU IRQs.
> +static void bcm2836_mask_gpu_irq(struct irq_data *d)
> +{
> +}
> +
> +static void bcm2836_unmask_gpu_irq(struct irq_data *d)
> +{
> +}
If the IRQs can't be masked, should these functions actually be implemented?
> +static void __exception_irq_entry bcm2836_handle_irq(struct pt_regs *regs)
> +{
> + int cpu = smp_processor_id();
> + u32 stat;
> +
> + stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
> + if (stat & 0x10) {
> + void __iomem *mailbox0 = (intc.base +
> + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
> + u32 mbox_val = readl(mailbox0);
> + u32 ipi = ffs(mbox_val) - 1;
> +
> + writel(1 << ipi, mailbox0);
> + handle_IPI(ipi, regs);
Given that bcm2836_send_ipi() is #ifdef CONFIG_SMP, should this code be too?
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Warren <swarren@wwwdotorg.org>
To: Eric Anholt <eric@anholt.net>, linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org, Jason Cooper <jason@lakedaemon.net>,
Andrea Merello <andrea.merello@gmail.com>,
Lee Jones <lee@kernel.org>,
linux-kernel@vger.kernel.org,
linux-rpi-kernel@lists.infradead.org,
Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [PATCH 4/4] irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2.
Date: Fri, 10 Jul 2015 23:13:15 -0600 [thread overview]
Message-ID: <55A0A5EB.4090007@wwwdotorg.org> (raw)
In-Reply-To: <1436303617-17185-5-git-send-email-eric@anholt.net>
On 07/07/2015 03:13 PM, Eric Anholt wrote:
> This interrupt controller is the new root interrupt controller with
> the timer, PMU events, and IPIs, and the bcm2835's interrupt
> controller is chained off of it to handle the peripherals.
>
> SMP IPI support was mostly written by Andrea Merello, while I wrote
> most of the rest of the IRQ handling.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Eric Anholt <eric@anholt.net>
I'd expect the git patch author to be Andrea if he wrote the original
patch and you enhanced it.
> diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c
> +struct arm_local_intc {
> + struct irq_domain *domain;
> + void __iomem *base;
> +};
> +
> +static struct arm_local_intc intc __read_mostly;
It'd be nice to give everything (types, functions, variables) a
consistent symbol prefix; bcm2836_arm_irqchip_ sounds like a good
bikeshed to me, but perhaps just propagating the above arm_local_ to the
functions too would be good, although that seems to risk symbol name
collisions with other ARM SoCs.
> +static void bcm2836_mask_per_cpu_irq(unsigned int reg, unsigned int bit)
> +{
> + void __iomem *reg_base = intc.base + reg;
> + unsigned int i;
> +
> + for (i = 0; i < 4; i++)
Is "4" there the CPU count? Perhaps this should use one of the Linux
APIs to query the CPU count rather than hard-coding it?
Should per-CPU IRQs automatically be masked on all CPUs at once, or only
on the current CPU? A very quick look at the ARM GIC driver implies it
doesn't iterate over all CPUs when masking per-CPU IRQs.
> +static void bcm2836_mask_gpu_irq(struct irq_data *d)
> +{
> +}
> +
> +static void bcm2836_unmask_gpu_irq(struct irq_data *d)
> +{
> +}
If the IRQs can't be masked, should these functions actually be implemented?
> +static void __exception_irq_entry bcm2836_handle_irq(struct pt_regs *regs)
> +{
> + int cpu = smp_processor_id();
> + u32 stat;
> +
> + stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
> + if (stat & 0x10) {
> + void __iomem *mailbox0 = (intc.base +
> + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
> + u32 mbox_val = readl(mailbox0);
> + u32 ipi = ffs(mbox_val) - 1;
> +
> + writel(1 << ipi, mailbox0);
> + handle_IPI(ipi, regs);
Given that bcm2836_send_ipi() is #ifdef CONFIG_SMP, should this code be too?
WARNING: multiple messages have this Message-ID (diff)
From: swarren@wwwdotorg.org (Stephen Warren)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/4] irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2.
Date: Fri, 10 Jul 2015 23:13:15 -0600 [thread overview]
Message-ID: <55A0A5EB.4090007@wwwdotorg.org> (raw)
In-Reply-To: <1436303617-17185-5-git-send-email-eric@anholt.net>
On 07/07/2015 03:13 PM, Eric Anholt wrote:
> This interrupt controller is the new root interrupt controller with
> the timer, PMU events, and IPIs, and the bcm2835's interrupt
> controller is chained off of it to handle the peripherals.
>
> SMP IPI support was mostly written by Andrea Merello, while I wrote
> most of the rest of the IRQ handling.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Eric Anholt <eric@anholt.net>
I'd expect the git patch author to be Andrea if he wrote the original
patch and you enhanced it.
> diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c
> +struct arm_local_intc {
> + struct irq_domain *domain;
> + void __iomem *base;
> +};
> +
> +static struct arm_local_intc intc __read_mostly;
It'd be nice to give everything (types, functions, variables) a
consistent symbol prefix; bcm2836_arm_irqchip_ sounds like a good
bikeshed to me, but perhaps just propagating the above arm_local_ to the
functions too would be good, although that seems to risk symbol name
collisions with other ARM SoCs.
> +static void bcm2836_mask_per_cpu_irq(unsigned int reg, unsigned int bit)
> +{
> + void __iomem *reg_base = intc.base + reg;
> + unsigned int i;
> +
> + for (i = 0; i < 4; i++)
Is "4" there the CPU count? Perhaps this should use one of the Linux
APIs to query the CPU count rather than hard-coding it?
Should per-CPU IRQs automatically be masked on all CPUs at once, or only
on the current CPU? A very quick look@the ARM GIC driver implies it
doesn't iterate over all CPUs when masking per-CPU IRQs.
> +static void bcm2836_mask_gpu_irq(struct irq_data *d)
> +{
> +}
> +
> +static void bcm2836_unmask_gpu_irq(struct irq_data *d)
> +{
> +}
If the IRQs can't be masked, should these functions actually be implemented?
> +static void __exception_irq_entry bcm2836_handle_irq(struct pt_regs *regs)
> +{
> + int cpu = smp_processor_id();
> + u32 stat;
> +
> + stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
> + if (stat & 0x10) {
> + void __iomem *mailbox0 = (intc.base +
> + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
> + u32 mbox_val = readl(mailbox0);
> + u32 ipi = ffs(mbox_val) - 1;
> +
> + writel(1 << ipi, mailbox0);
> + handle_IPI(ipi, regs);
Given that bcm2836_send_ipi() is #ifdef CONFIG_SMP, should this code be too?
next prev parent reply other threads:[~2015-07-11 6:29 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-07 21:13 Raspberry Pi 2 support, part 1: Interrupt controller Eric Anholt
2015-07-07 21:13 ` Eric Anholt
2015-07-07 21:13 ` Eric Anholt
2015-07-07 21:13 ` [PATCH 1/4] irqchip: bcm2835: Refactor handle_IRQ() calls out of MAKE_HWIRQ Eric Anholt
2015-07-07 21:13 ` Eric Anholt
2015-07-07 21:13 ` Eric Anholt
2015-07-07 21:13 ` [PATCH 2/4] irqchip: bcm2835: If a parent interrupt is registered, chain from it Eric Anholt
2015-07-07 21:13 ` Eric Anholt
2015-07-07 21:13 ` [PATCH 3/4] irqchip: Add documentation for the bcm2836 interrupt controller Eric Anholt
2015-07-07 21:13 ` Eric Anholt
2015-07-07 21:13 ` Eric Anholt
2015-07-11 4:57 ` Stephen Warren
2015-07-11 4:57 ` Stephen Warren
2015-07-11 4:57 ` Stephen Warren
2015-07-11 6:01 ` Eric Anholt
2015-07-11 6:01 ` Eric Anholt
2015-07-11 6:01 ` Eric Anholt
2015-07-14 5:08 ` Stephen Warren
2015-07-14 5:08 ` Stephen Warren
2015-07-14 5:08 ` Stephen Warren
2015-07-07 21:13 ` [PATCH 4/4] irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2 Eric Anholt
2015-07-07 21:13 ` Eric Anholt
2015-07-07 21:13 ` Eric Anholt
2015-07-11 5:13 ` Stephen Warren [this message]
2015-07-11 5:13 ` Stephen Warren
2015-07-11 5:13 ` Stephen Warren
2015-07-11 7:51 ` Thomas Gleixner
2015-07-11 7:51 ` Thomas Gleixner
2015-07-11 7:51 ` Thomas Gleixner
2015-07-13 16:06 ` Eric Anholt
2015-07-13 16:06 ` Eric Anholt
2015-07-14 5:09 ` Stephen Warren
2015-07-14 5:09 ` Stephen Warren
2015-07-14 5:09 ` Stephen Warren
2015-07-13 18:48 ` Eric Anholt
2015-07-13 18:48 ` Eric Anholt
2015-07-13 18:48 ` Eric Anholt
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