From: Frank Li <Frank.li@nxp.com> To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: "Richard Zhu" <hongxing.zhu@nxp.com>, "Lucas Stach" <l.stach@pengutronix.de>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Rob Herring" <robh@kernel.org>, "Bjorn Helgaas" <bhelgaas@google.com>, "Shawn Guo" <shawnguo@kernel.org>, "Sascha Hauer" <s.hauer@pengutronix.de>, "Pengutronix Kernel Team" <kernel@pengutronix.de>, "Fabio Estevam" <festevam@gmail.com>, "NXP Linux Team" <linux-imx@nxp.com>, "Philipp Zabel" <p.zabel@pengutronix.de>, "Liam Girdwood" <lgirdwood@gmail.com>, "Mark Brown" <broonie@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Conor Dooley" <conor+dt@kernel.org>, linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 11/11] PCI: imx6: Add i.MX8Q PCIe support Date: Mon, 29 Apr 2024 13:56:58 -0400 [thread overview] Message-ID: <Zi/faud9ZrlsA9us@lizhi-Precision-Tower-5810> (raw) In-Reply-To: <20240427114736.GO1981@thinkpad> On Sat, Apr 27, 2024 at 05:17:36PM +0530, Manivannan Sadhasivam wrote: > On Tue, Apr 02, 2024 at 10:33:47AM -0400, Frank Li wrote: > > From: Richard Zhu <hongxing.zhu@nxp.com> > > > > Add i.MX8Q (i.MX8QM, i.MX8QXP and i.MX8DXL) PCIe support. > > > > Add some info like IP version, PCIe Gen, how different the code support > comparted to previous SoCs etc... > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > drivers/pci/controller/dwc/pcie-imx.c | 54 +++++++++++++++++++++++++++++++++++ > > 1 file changed, 54 insertions(+) > > > > diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c > > index 378808262d16b..af7c79e869e70 100644 > > --- a/drivers/pci/controller/dwc/pcie-imx.c > > +++ b/drivers/pci/controller/dwc/pcie-imx.c > > @@ -30,6 +30,7 @@ > > #include <linux/interrupt.h> > > #include <linux/reset.h> > > #include <linux/phy/phy.h> > > +#include <linux/phy/pcie.h> > > #include <linux/pm_domain.h> > > #include <linux/pm_runtime.h> > > > > @@ -81,6 +82,7 @@ enum imx_pcie_variants { > > IMX8MQ, > > IMX8MM, > > IMX8MP, > > + IMX8Q, > > IMX95, > > IMX8MQ_EP, > > IMX8MM_EP, > > @@ -96,6 +98,7 @@ enum imx_pcie_variants { > > #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) > > #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) > > #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) > > +#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8) > > > > #define imx_check_flag(pci, val) (pci->drvdata->flags & val) > > > > @@ -132,6 +135,7 @@ struct imx_pcie { > > struct regmap *iomuxc_gpr; > > u16 msi_ctrl; > > u32 controller_id; > > + u32 local_addr; > > struct reset_control *pciephy_reset; > > struct reset_control *apps_reset; > > struct reset_control *turnoff_reset; > > @@ -402,6 +406,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie) > > if (!drvdata->mode_mask[id]) > > id = 0; > > > > + /* If mode_mask is 0, means use phy driver to set mode */ > > + if (!drvdata->mode_mask[id]) > > + return; > > There is already a check above for 0 mode_mask. Please consolidate. > > > + > > mask = drvdata->mode_mask[id]; > > val = mode << (ffs(mask) - 1); > > > > @@ -957,6 +965,7 @@ static void imx_pcie_ltssm_enable(struct device *dev) > > struct imx_pcie *imx_pcie = dev_get_drvdata(dev); > > const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; > > > > + phy_set_speed(imx_pcie->phy, PCI_EXP_LNKCAP_SLS_2_5GB); > > if (drvdata->ltssm_mask) > > regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, > > drvdata->ltssm_mask); > > @@ -969,6 +978,7 @@ static void imx_pcie_ltssm_disable(struct device *dev) > > struct imx_pcie *imx_pcie = dev_get_drvdata(dev); > > const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; > > > > + phy_set_speed(imx_pcie->phy, 0); > > if (drvdata->ltssm_mask) > > regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, > > drvdata->ltssm_mask, 0); > > @@ -1104,6 +1114,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) > > goto err_clk_disable; > > } > > > > + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); > > + if (ret) { > > + dev_err(dev, "unable to set pcie PHY mode\n"); > > + goto err_phy_off; > > + } > > This is not i.MX8Q specific. Please add it in a separate patch. > > > + > > ret = phy_power_on(imx_pcie->phy); > > if (ret) { > > dev_err(dev, "waiting for PHY ready timeout!\n"); > > @@ -1154,6 +1170,28 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp) > > regulator_disable(imx_pcie->vpcie); > > } > > > > +static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) > > +{ > > + struct imx_pcie *imx_pcie = to_imx_pcie(pcie); > > + struct dw_pcie_ep *ep = &pcie->ep; > > + struct dw_pcie_rp *pp = &pcie->pp; > > + struct resource_entry *entry; > > + unsigned int offset; > > + > > + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) > > This flag should be documented in the commit message. > > > + return cpu_addr; > > + > > + if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { > > + offset = ep->phys_base; > > + } else { > > + entry = resource_list_first_type(&pp->bridge->windows, > > + IORESOURCE_MEM); > > Check for NULL entry. > > > + offset = entry->res->start; > > + } > > + > > + return (cpu_addr + imx_pcie->local_addr - offset); > > +} > > + > > static const struct dw_pcie_host_ops imx_pcie_host_ops = { > > .init = imx_pcie_host_init, > > .deinit = imx_pcie_host_exit, > > @@ -1162,6 +1200,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_ops = { > > static const struct dw_pcie_ops dw_pcie_ops = { > > .start_link = imx_pcie_start_link, > > .stop_link = imx_pcie_stop_link, > > + .cpu_addr_fixup = imx_pcie_cpu_addr_fixup, > > }; > > > > static void imx_pcie_ep_init(struct dw_pcie_ep *ep) > > @@ -1481,6 +1520,12 @@ static int imx_pcie_probe(struct platform_device *pdev) > > "Failed to get PCIEPHY reset control\n"); > > } > > > > + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) { > > + ret = of_property_read_u32(node, "fsl,local-address", &imx_pcie->local_addr); > > + if (ret) > > + return dev_err_probe(dev, ret, "Failed to get local-address"); > > Is it OK to continue? No, if no "fsl,local-address" for iMX8QM/QXP, address map will be wrong. Frank > > - Mani > > -- > மணிவண்ணன் சதாசிவம்
WARNING: multiple messages have this Message-ID (diff)
From: Frank Li <Frank.li@nxp.com> To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: "Richard Zhu" <hongxing.zhu@nxp.com>, "Lucas Stach" <l.stach@pengutronix.de>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Rob Herring" <robh@kernel.org>, "Bjorn Helgaas" <bhelgaas@google.com>, "Shawn Guo" <shawnguo@kernel.org>, "Sascha Hauer" <s.hauer@pengutronix.de>, "Pengutronix Kernel Team" <kernel@pengutronix.de>, "Fabio Estevam" <festevam@gmail.com>, "NXP Linux Team" <linux-imx@nxp.com>, "Philipp Zabel" <p.zabel@pengutronix.de>, "Liam Girdwood" <lgirdwood@gmail.com>, "Mark Brown" <broonie@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Conor Dooley" <conor+dt@kernel.org>, linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 11/11] PCI: imx6: Add i.MX8Q PCIe support Date: Mon, 29 Apr 2024 13:56:58 -0400 [thread overview] Message-ID: <Zi/faud9ZrlsA9us@lizhi-Precision-Tower-5810> (raw) In-Reply-To: <20240427114736.GO1981@thinkpad> On Sat, Apr 27, 2024 at 05:17:36PM +0530, Manivannan Sadhasivam wrote: > On Tue, Apr 02, 2024 at 10:33:47AM -0400, Frank Li wrote: > > From: Richard Zhu <hongxing.zhu@nxp.com> > > > > Add i.MX8Q (i.MX8QM, i.MX8QXP and i.MX8DXL) PCIe support. > > > > Add some info like IP version, PCIe Gen, how different the code support > comparted to previous SoCs etc... > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > drivers/pci/controller/dwc/pcie-imx.c | 54 +++++++++++++++++++++++++++++++++++ > > 1 file changed, 54 insertions(+) > > > > diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c > > index 378808262d16b..af7c79e869e70 100644 > > --- a/drivers/pci/controller/dwc/pcie-imx.c > > +++ b/drivers/pci/controller/dwc/pcie-imx.c > > @@ -30,6 +30,7 @@ > > #include <linux/interrupt.h> > > #include <linux/reset.h> > > #include <linux/phy/phy.h> > > +#include <linux/phy/pcie.h> > > #include <linux/pm_domain.h> > > #include <linux/pm_runtime.h> > > > > @@ -81,6 +82,7 @@ enum imx_pcie_variants { > > IMX8MQ, > > IMX8MM, > > IMX8MP, > > + IMX8Q, > > IMX95, > > IMX8MQ_EP, > > IMX8MM_EP, > > @@ -96,6 +98,7 @@ enum imx_pcie_variants { > > #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) > > #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) > > #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) > > +#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8) > > > > #define imx_check_flag(pci, val) (pci->drvdata->flags & val) > > > > @@ -132,6 +135,7 @@ struct imx_pcie { > > struct regmap *iomuxc_gpr; > > u16 msi_ctrl; > > u32 controller_id; > > + u32 local_addr; > > struct reset_control *pciephy_reset; > > struct reset_control *apps_reset; > > struct reset_control *turnoff_reset; > > @@ -402,6 +406,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie) > > if (!drvdata->mode_mask[id]) > > id = 0; > > > > + /* If mode_mask is 0, means use phy driver to set mode */ > > + if (!drvdata->mode_mask[id]) > > + return; > > There is already a check above for 0 mode_mask. Please consolidate. > > > + > > mask = drvdata->mode_mask[id]; > > val = mode << (ffs(mask) - 1); > > > > @@ -957,6 +965,7 @@ static void imx_pcie_ltssm_enable(struct device *dev) > > struct imx_pcie *imx_pcie = dev_get_drvdata(dev); > > const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; > > > > + phy_set_speed(imx_pcie->phy, PCI_EXP_LNKCAP_SLS_2_5GB); > > if (drvdata->ltssm_mask) > > regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, > > drvdata->ltssm_mask); > > @@ -969,6 +978,7 @@ static void imx_pcie_ltssm_disable(struct device *dev) > > struct imx_pcie *imx_pcie = dev_get_drvdata(dev); > > const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; > > > > + phy_set_speed(imx_pcie->phy, 0); > > if (drvdata->ltssm_mask) > > regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, > > drvdata->ltssm_mask, 0); > > @@ -1104,6 +1114,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) > > goto err_clk_disable; > > } > > > > + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); > > + if (ret) { > > + dev_err(dev, "unable to set pcie PHY mode\n"); > > + goto err_phy_off; > > + } > > This is not i.MX8Q specific. Please add it in a separate patch. > > > + > > ret = phy_power_on(imx_pcie->phy); > > if (ret) { > > dev_err(dev, "waiting for PHY ready timeout!\n"); > > @@ -1154,6 +1170,28 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp) > > regulator_disable(imx_pcie->vpcie); > > } > > > > +static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) > > +{ > > + struct imx_pcie *imx_pcie = to_imx_pcie(pcie); > > + struct dw_pcie_ep *ep = &pcie->ep; > > + struct dw_pcie_rp *pp = &pcie->pp; > > + struct resource_entry *entry; > > + unsigned int offset; > > + > > + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) > > This flag should be documented in the commit message. > > > + return cpu_addr; > > + > > + if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { > > + offset = ep->phys_base; > > + } else { > > + entry = resource_list_first_type(&pp->bridge->windows, > > + IORESOURCE_MEM); > > Check for NULL entry. > > > + offset = entry->res->start; > > + } > > + > > + return (cpu_addr + imx_pcie->local_addr - offset); > > +} > > + > > static const struct dw_pcie_host_ops imx_pcie_host_ops = { > > .init = imx_pcie_host_init, > > .deinit = imx_pcie_host_exit, > > @@ -1162,6 +1200,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_ops = { > > static const struct dw_pcie_ops dw_pcie_ops = { > > .start_link = imx_pcie_start_link, > > .stop_link = imx_pcie_stop_link, > > + .cpu_addr_fixup = imx_pcie_cpu_addr_fixup, > > }; > > > > static void imx_pcie_ep_init(struct dw_pcie_ep *ep) > > @@ -1481,6 +1520,12 @@ static int imx_pcie_probe(struct platform_device *pdev) > > "Failed to get PCIEPHY reset control\n"); > > } > > > > + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) { > > + ret = of_property_read_u32(node, "fsl,local-address", &imx_pcie->local_addr); > > + if (ret) > > + return dev_err_probe(dev, ret, "Failed to get local-address"); > > Is it OK to continue? No, if no "fsl,local-address" for iMX8QM/QXP, address map will be wrong. Frank > > - Mani > > -- > மணிவண்ணன் சதாசிவம் _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-04-29 17:57 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-02 14:33 [PATCH v3 00/11] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li 2024-04-02 14:33 ` Frank Li 2024-04-02 14:33 ` [PATCH v3 01/11] PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode Frank Li 2024-04-02 14:33 ` Frank Li 2024-04-27 9:00 ` Manivannan Sadhasivam 2024-04-27 9:00 ` Manivannan Sadhasivam 2024-04-29 14:53 ` Frank Li 2024-04-29 14:53 ` Frank Li 2024-04-02 14:33 ` [PATCH v3 02/11] PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI Frank Li 2024-04-02 14:33 ` Frank Li 2024-04-27 9:23 ` Manivannan Sadhasivam 2024-04-27 9:23 ` Manivannan Sadhasivam 2024-04-29 15:58 ` Frank Li 2024-04-29 15:58 ` Frank Li 2024-04-02 14:33 ` [PATCH v3 03/11] PCI: imx6: Rename imx6_* with imx_* Frank Li 2024-04-02 14:33 ` Frank Li 2024-04-27 9:29 ` Manivannan Sadhasivam 2024-04-27 9:29 ` Manivannan Sadhasivam 2024-04-02 14:33 ` [PATCH v3 04/11] PCI: imx6: Rename pci-imx6.c to pcie-imx.c Frank Li 2024-04-02 14:33 ` Frank Li 2024-04-27 9:31 ` Manivannan Sadhasivam 2024-04-27 9:31 ` Manivannan Sadhasivam 2024-04-29 16:01 ` Frank Li 2024-04-29 16:01 ` Frank Li 2024-04-02 14:33 ` [PATCH v3 05/11] MAINTAINERS: pci: imx: update imx6* to imx* since rename driver file Frank Li 2024-04-02 14:33 ` Frank Li 2024-04-27 9:33 ` Manivannan Sadhasivam 2024-04-27 9:33 ` Manivannan Sadhasivam 2024-04-29 15:03 ` Rob Herring 2024-04-29 15:03 ` Rob Herring 2024-04-02 14:33 ` [PATCH v3 06/11] PCI: imx: Simplify switch-case logic by involve set_ref_clk callback Frank Li 2024-04-02 14:33 ` Frank Li 2024-04-27 9:54 ` Manivannan Sadhasivam 2024-04-27 9:54 ` Manivannan Sadhasivam 2024-04-02 14:33 ` [PATCH v3 07/11] PCI: imx: Simplify switch-case logic by involve core_reset callback Frank Li 2024-04-02 14:33 ` Frank Li 2024-04-27 10:19 ` Manivannan Sadhasivam 2024-04-27 10:19 ` Manivannan Sadhasivam 2024-04-29 16:38 ` Frank Li 2024-04-29 16:38 ` Frank Li 2024-04-02 14:33 ` [PATCH v3 08/11] PCI: imx: Config look up table(LUT) to support MSI ITS and IOMMU for i.MX95 Frank Li 2024-04-02 14:33 ` Frank Li 2024-04-27 11:36 ` Manivannan Sadhasivam 2024-04-27 11:36 ` Manivannan Sadhasivam 2024-04-29 15:06 ` Rob Herring 2024-04-29 15:06 ` Rob Herring 2024-04-29 17:00 ` Frank Li 2024-04-29 17:00 ` Frank Li 2024-04-29 15:08 ` Rob Herring 2024-04-29 15:08 ` Rob Herring 2024-04-02 14:33 ` [PATCH v3 09/11] PCI: imx: Consolidate redundant if-checks Frank Li 2024-04-02 14:33 ` Frank Li 2024-04-27 11:38 ` Manivannan Sadhasivam 2024-04-27 11:38 ` Manivannan Sadhasivam 2024-04-02 14:33 ` [PATCH v3 10/11] dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string Frank Li 2024-04-02 14:33 ` Frank Li 2024-04-29 15:48 ` Rob Herring 2024-04-29 15:48 ` Rob Herring 2024-04-29 21:23 ` Frank Li 2024-04-29 21:23 ` Frank Li 2024-05-07 14:55 ` Rob Herring 2024-05-07 14:55 ` Rob Herring 2024-04-02 14:33 ` [PATCH v3 11/11] PCI: imx6: Add i.MX8Q PCIe support Frank Li 2024-04-02 14:33 ` Frank Li 2024-04-27 11:47 ` Manivannan Sadhasivam 2024-04-27 11:47 ` Manivannan Sadhasivam 2024-04-29 17:56 ` Frank Li [this message] 2024-04-29 17:56 ` Frank Li 2024-04-16 14:07 ` [PATCH v3 00/11] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li 2024-04-16 14:07 ` Frank Li 2024-04-25 11:12 ` Manivannan Sadhasivam 2024-04-25 11:12 ` Manivannan Sadhasivam 2024-04-23 14:23 ` Frank Li 2024-04-23 14:23 ` Frank Li
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