From: zhaoshenglong@huawei.com (Shannon Zhao)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 12/22] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register
Date: Fri, 11 Sep 2015 16:55:05 +0800 [thread overview]
Message-ID: <1441961715-11688-13-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1441961715-11688-1-git-send-email-zhaoshenglong@huawei.com>
From: Shannon Zhao <shannon.zhao@linaro.org>
Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMCNTENSET or PMCNTENCLR register.
When writing to PMCNTENSET, call perf_event_enable to enable the perf
event. When writing to PMCNTENCLR, call perf_event_disable to disable
the perf event.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 46 +++++++++++++++++++++++++++++++++++++++++----
include/kvm/arm_pmu.h | 4 ++++
virt/kvm/arm/pmu.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 94 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f8d7de0..8307189 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -293,6 +293,24 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
val);
break;
}
+ case PMCNTENSET_EL0: {
+ val = *vcpu_reg(vcpu, p->Rt);
+ kvm_pmu_enable_counter(vcpu, val);
+ /*Value 1 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means
+ * corresponding counter enabled */
+ vcpu_sys_reg(vcpu, r->reg) |= val;
+ vcpu_sys_reg(vcpu, PMCNTENCLR_EL0) |= val;
+ break;
+ }
+ case PMCNTENCLR_EL0: {
+ val = *vcpu_reg(vcpu, p->Rt);
+ kvm_pmu_disable_counter(vcpu, val);
+ /*Value 0 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means
+ * corresponding counter disabled */
+ vcpu_sys_reg(vcpu, r->reg) &= ~val;
+ vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
+ break;
+ }
case PMCR_EL0: {
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
@@ -525,10 +543,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmu_regs, reset_pmcr, PMCR_EL0, },
/* PMCNTENSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMCNTENSET_EL0 },
/* PMCNTENCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMCNTENCLR_EL0 },
/* PMOVSCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
trap_raz_wi },
@@ -749,6 +767,24 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
val);
break;
}
+ case c9_PMCNTENSET: {
+ val = *vcpu_reg(vcpu, p->Rt);
+ kvm_pmu_enable_counter(vcpu, val);
+ /*Value 1 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means
+ * corresponding counter enabled */
+ vcpu_cp15(vcpu, r->reg) |= val;
+ vcpu_cp15(vcpu, c9_PMCNTENCLR) |= val;
+ break;
+ }
+ case c9_PMCNTENCLR: {
+ val = *vcpu_reg(vcpu, p->Rt);
+ kvm_pmu_disable_counter(vcpu, val);
+ /*Value 0 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means
+ * corresponding counter disabled */
+ vcpu_cp15(vcpu, r->reg) &= ~val;
+ vcpu_cp15(vcpu, c9_PMCNTENSET) &= ~val;
+ break;
+ }
case c9_PMCR: {
/* Only update writeable bits of PMCR */
val = vcpu_cp15(vcpu, r->reg);
@@ -817,8 +853,10 @@ static const struct sys_reg_desc cp15_regs[] = {
/* PMU */
{ Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmu_cp15_regs,
reset_pmcr, c9_PMCR },
- { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMCNTENSET },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMCNTENCLR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
reset_unknown_cp15, c9_PMSELR },
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 387ec6f..59e70af 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -39,6 +39,8 @@ struct kvm_pmu {
#ifdef CONFIG_KVM_ARM_PMU
unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
unsigned long select_idx);
+void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val);
+void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, unsigned long val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data,
unsigned long select_idx);
#else
@@ -47,6 +49,8 @@ unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
{
return 0;
}
+void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val) {}
+void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, unsigned long val) {}
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data,
unsigned long select_idx) {}
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 0c7fe5c..c6cdc4e 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -115,6 +115,54 @@ unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
}
/**
+ * kvm_pmu_enable_counter - enable selected PMU counter
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMCNTENSET register
+ *
+ * Call perf_event_enable to start counting the perf event
+ */
+void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, unsigned long val)
+{
+ int i;
+ struct kvm_pmu *pmu = &vcpu->arch.pmu;
+ struct kvm_pmc *pmc;
+
+ for (i = 0; i < 32; i++) {
+ if ((val >> i) & 0x1) {
+ pmc = &pmu->pmc[i];
+ if (pmc->perf_event) {
+ perf_event_enable(pmc->perf_event);
+ if (pmc->perf_event->state
+ != PERF_EVENT_STATE_ACTIVE)
+ kvm_debug("fail to enable event\n");
+ }
+ }
+ }
+}
+
+/**
+ * kvm_pmu_disable_counter - disable selected PMU counter
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMCNTENCLR register
+ *
+ * Call perf_event_disable to stop counting the perf event
+ */
+void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val)
+{
+ int i;
+ struct kvm_pmu *pmu = &vcpu->arch.pmu;
+ struct kvm_pmc *pmc;
+
+ for (i = 0; i < 32; i++) {
+ if ((val >> i) & 0x1) {
+ pmc = &pmu->pmc[i];
+ if (pmc->perf_event)
+ perf_event_disable(pmc->perf_event);
+ }
+ }
+}
+
+/**
* kvm_pmu_find_hw_event - find hardware event
* @pmu: The pmu pointer
* @event_select: The number of selected event type
--
2.0.4
WARNING: multiple messages have this Message-ID (diff)
From: Shannon Zhao <zhaoshenglong@huawei.com>
To: kvmarm@lists.cs.columbia.edu
Cc: kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com,
linux-arm-kernel@lists.infradead.org, shannon.zhao@linaro.org
Subject: [PATCH v2 12/22] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register
Date: Fri, 11 Sep 2015 16:55:05 +0800 [thread overview]
Message-ID: <1441961715-11688-13-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1441961715-11688-1-git-send-email-zhaoshenglong@huawei.com>
From: Shannon Zhao <shannon.zhao@linaro.org>
Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMCNTENSET or PMCNTENCLR register.
When writing to PMCNTENSET, call perf_event_enable to enable the perf
event. When writing to PMCNTENCLR, call perf_event_disable to disable
the perf event.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 46 +++++++++++++++++++++++++++++++++++++++++----
include/kvm/arm_pmu.h | 4 ++++
virt/kvm/arm/pmu.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 94 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f8d7de0..8307189 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -293,6 +293,24 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
val);
break;
}
+ case PMCNTENSET_EL0: {
+ val = *vcpu_reg(vcpu, p->Rt);
+ kvm_pmu_enable_counter(vcpu, val);
+ /*Value 1 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means
+ * corresponding counter enabled */
+ vcpu_sys_reg(vcpu, r->reg) |= val;
+ vcpu_sys_reg(vcpu, PMCNTENCLR_EL0) |= val;
+ break;
+ }
+ case PMCNTENCLR_EL0: {
+ val = *vcpu_reg(vcpu, p->Rt);
+ kvm_pmu_disable_counter(vcpu, val);
+ /*Value 0 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means
+ * corresponding counter disabled */
+ vcpu_sys_reg(vcpu, r->reg) &= ~val;
+ vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
+ break;
+ }
case PMCR_EL0: {
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
@@ -525,10 +543,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmu_regs, reset_pmcr, PMCR_EL0, },
/* PMCNTENSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMCNTENSET_EL0 },
/* PMCNTENCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMCNTENCLR_EL0 },
/* PMOVSCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
trap_raz_wi },
@@ -749,6 +767,24 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
val);
break;
}
+ case c9_PMCNTENSET: {
+ val = *vcpu_reg(vcpu, p->Rt);
+ kvm_pmu_enable_counter(vcpu, val);
+ /*Value 1 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means
+ * corresponding counter enabled */
+ vcpu_cp15(vcpu, r->reg) |= val;
+ vcpu_cp15(vcpu, c9_PMCNTENCLR) |= val;
+ break;
+ }
+ case c9_PMCNTENCLR: {
+ val = *vcpu_reg(vcpu, p->Rt);
+ kvm_pmu_disable_counter(vcpu, val);
+ /*Value 0 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means
+ * corresponding counter disabled */
+ vcpu_cp15(vcpu, r->reg) &= ~val;
+ vcpu_cp15(vcpu, c9_PMCNTENSET) &= ~val;
+ break;
+ }
case c9_PMCR: {
/* Only update writeable bits of PMCR */
val = vcpu_cp15(vcpu, r->reg);
@@ -817,8 +853,10 @@ static const struct sys_reg_desc cp15_regs[] = {
/* PMU */
{ Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmu_cp15_regs,
reset_pmcr, c9_PMCR },
- { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMCNTENSET },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMCNTENCLR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
reset_unknown_cp15, c9_PMSELR },
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 387ec6f..59e70af 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -39,6 +39,8 @@ struct kvm_pmu {
#ifdef CONFIG_KVM_ARM_PMU
unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
unsigned long select_idx);
+void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val);
+void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, unsigned long val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data,
unsigned long select_idx);
#else
@@ -47,6 +49,8 @@ unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
{
return 0;
}
+void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val) {}
+void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, unsigned long val) {}
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data,
unsigned long select_idx) {}
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 0c7fe5c..c6cdc4e 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -115,6 +115,54 @@ unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
}
/**
+ * kvm_pmu_enable_counter - enable selected PMU counter
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMCNTENSET register
+ *
+ * Call perf_event_enable to start counting the perf event
+ */
+void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, unsigned long val)
+{
+ int i;
+ struct kvm_pmu *pmu = &vcpu->arch.pmu;
+ struct kvm_pmc *pmc;
+
+ for (i = 0; i < 32; i++) {
+ if ((val >> i) & 0x1) {
+ pmc = &pmu->pmc[i];
+ if (pmc->perf_event) {
+ perf_event_enable(pmc->perf_event);
+ if (pmc->perf_event->state
+ != PERF_EVENT_STATE_ACTIVE)
+ kvm_debug("fail to enable event\n");
+ }
+ }
+ }
+}
+
+/**
+ * kvm_pmu_disable_counter - disable selected PMU counter
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMCNTENCLR register
+ *
+ * Call perf_event_disable to stop counting the perf event
+ */
+void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val)
+{
+ int i;
+ struct kvm_pmu *pmu = &vcpu->arch.pmu;
+ struct kvm_pmc *pmc;
+
+ for (i = 0; i < 32; i++) {
+ if ((val >> i) & 0x1) {
+ pmc = &pmu->pmc[i];
+ if (pmc->perf_event)
+ perf_event_disable(pmc->perf_event);
+ }
+ }
+}
+
+/**
* kvm_pmu_find_hw_event - find hardware event
* @pmu: The pmu pointer
* @event_select: The number of selected event type
--
2.0.4
WARNING: multiple messages have this Message-ID (diff)
From: Shannon Zhao <zhaoshenglong@huawei.com>
To: <kvmarm@lists.cs.columbia.edu>
Cc: kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com,
linux-arm-kernel@lists.infradead.org, shannon.zhao@linaro.org
Subject: [PATCH v2 12/22] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register
Date: Fri, 11 Sep 2015 16:55:05 +0800 [thread overview]
Message-ID: <1441961715-11688-13-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1441961715-11688-1-git-send-email-zhaoshenglong@huawei.com>
From: Shannon Zhao <shannon.zhao@linaro.org>
Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMCNTENSET or PMCNTENCLR register.
When writing to PMCNTENSET, call perf_event_enable to enable the perf
event. When writing to PMCNTENCLR, call perf_event_disable to disable
the perf event.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 46 +++++++++++++++++++++++++++++++++++++++++----
include/kvm/arm_pmu.h | 4 ++++
virt/kvm/arm/pmu.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 94 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f8d7de0..8307189 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -293,6 +293,24 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
val);
break;
}
+ case PMCNTENSET_EL0: {
+ val = *vcpu_reg(vcpu, p->Rt);
+ kvm_pmu_enable_counter(vcpu, val);
+ /*Value 1 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means
+ * corresponding counter enabled */
+ vcpu_sys_reg(vcpu, r->reg) |= val;
+ vcpu_sys_reg(vcpu, PMCNTENCLR_EL0) |= val;
+ break;
+ }
+ case PMCNTENCLR_EL0: {
+ val = *vcpu_reg(vcpu, p->Rt);
+ kvm_pmu_disable_counter(vcpu, val);
+ /*Value 0 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means
+ * corresponding counter disabled */
+ vcpu_sys_reg(vcpu, r->reg) &= ~val;
+ vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
+ break;
+ }
case PMCR_EL0: {
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
@@ -525,10 +543,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmu_regs, reset_pmcr, PMCR_EL0, },
/* PMCNTENSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMCNTENSET_EL0 },
/* PMCNTENCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMCNTENCLR_EL0 },
/* PMOVSCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
trap_raz_wi },
@@ -749,6 +767,24 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
val);
break;
}
+ case c9_PMCNTENSET: {
+ val = *vcpu_reg(vcpu, p->Rt);
+ kvm_pmu_enable_counter(vcpu, val);
+ /*Value 1 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means
+ * corresponding counter enabled */
+ vcpu_cp15(vcpu, r->reg) |= val;
+ vcpu_cp15(vcpu, c9_PMCNTENCLR) |= val;
+ break;
+ }
+ case c9_PMCNTENCLR: {
+ val = *vcpu_reg(vcpu, p->Rt);
+ kvm_pmu_disable_counter(vcpu, val);
+ /*Value 0 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means
+ * corresponding counter disabled */
+ vcpu_cp15(vcpu, r->reg) &= ~val;
+ vcpu_cp15(vcpu, c9_PMCNTENSET) &= ~val;
+ break;
+ }
case c9_PMCR: {
/* Only update writeable bits of PMCR */
val = vcpu_cp15(vcpu, r->reg);
@@ -817,8 +853,10 @@ static const struct sys_reg_desc cp15_regs[] = {
/* PMU */
{ Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmu_cp15_regs,
reset_pmcr, c9_PMCR },
- { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMCNTENSET },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMCNTENCLR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
reset_unknown_cp15, c9_PMSELR },
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 387ec6f..59e70af 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -39,6 +39,8 @@ struct kvm_pmu {
#ifdef CONFIG_KVM_ARM_PMU
unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
unsigned long select_idx);
+void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val);
+void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, unsigned long val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data,
unsigned long select_idx);
#else
@@ -47,6 +49,8 @@ unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
{
return 0;
}
+void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val) {}
+void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, unsigned long val) {}
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, unsigned long data,
unsigned long select_idx) {}
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 0c7fe5c..c6cdc4e 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -115,6 +115,54 @@ unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
}
/**
+ * kvm_pmu_enable_counter - enable selected PMU counter
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMCNTENSET register
+ *
+ * Call perf_event_enable to start counting the perf event
+ */
+void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, unsigned long val)
+{
+ int i;
+ struct kvm_pmu *pmu = &vcpu->arch.pmu;
+ struct kvm_pmc *pmc;
+
+ for (i = 0; i < 32; i++) {
+ if ((val >> i) & 0x1) {
+ pmc = &pmu->pmc[i];
+ if (pmc->perf_event) {
+ perf_event_enable(pmc->perf_event);
+ if (pmc->perf_event->state
+ != PERF_EVENT_STATE_ACTIVE)
+ kvm_debug("fail to enable event\n");
+ }
+ }
+ }
+}
+
+/**
+ * kvm_pmu_disable_counter - disable selected PMU counter
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMCNTENCLR register
+ *
+ * Call perf_event_disable to stop counting the perf event
+ */
+void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, unsigned long val)
+{
+ int i;
+ struct kvm_pmu *pmu = &vcpu->arch.pmu;
+ struct kvm_pmc *pmc;
+
+ for (i = 0; i < 32; i++) {
+ if ((val >> i) & 0x1) {
+ pmc = &pmu->pmc[i];
+ if (pmc->perf_event)
+ perf_event_disable(pmc->perf_event);
+ }
+ }
+}
+
+/**
* kvm_pmu_find_hw_event - find hardware event
* @pmu: The pmu pointer
* @event_select: The number of selected event type
--
2.0.4
next prev parent reply other threads:[~2015-09-11 8:55 UTC|newest]
Thread overview: 113+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-11 8:54 [PATCH v2 00/22] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` [PATCH v2 01/22] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` [PATCH v2 02/22] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 9:10 ` Marc Zyngier
2015-09-11 9:10 ` Marc Zyngier
2015-09-11 9:58 ` Shannon Zhao
2015-09-11 9:58 ` Shannon Zhao
2015-09-11 9:58 ` Shannon Zhao
2015-09-11 8:54 ` [PATCH v2 03/22] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` [PATCH v2 04/22] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 10:07 ` Marc Zyngier
2015-09-11 10:07 ` Marc Zyngier
2015-09-14 3:14 ` Shannon Zhao
2015-09-14 3:14 ` Shannon Zhao
2015-09-14 3:14 ` Shannon Zhao
2015-09-14 12:11 ` Marc Zyngier
2015-09-14 12:11 ` Marc Zyngier
2015-09-11 8:54 ` [PATCH v2 05/22] KVM: ARM64: Add a helper for CP15 registers reset to UNKNOWN Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 10:16 ` Marc Zyngier
2015-09-11 10:16 ` Marc Zyngier
2015-09-11 10:17 ` Marc Zyngier
2015-09-11 10:17 ` Marc Zyngier
2015-09-11 8:54 ` [PATCH v2 06/22] KVM: ARM64: Add reset and access handlers for PMSELR register Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 07/22] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 10:27 ` Marc Zyngier
2015-09-11 10:27 ` Marc Zyngier
2015-09-11 8:55 ` [PATCH v2 08/22] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 11:04 ` Marc Zyngier
2015-09-11 11:04 ` Marc Zyngier
2015-09-11 13:35 ` Shannon Zhao
2015-09-11 13:35 ` Shannon Zhao
2015-09-11 14:14 ` Marc Zyngier
2015-09-11 14:14 ` Marc Zyngier
2015-09-11 8:55 ` [PATCH v2 09/22] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 10/22] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 11/22] KVM: ARM64: Add reset and access handlers for PMCCNTR register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao [this message]
2015-09-11 8:55 ` [PATCH v2 12/22] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 13/22] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 14/22] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 15/22] KVM: ARM64: Add a helper for CP15 registers reset to specified value Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 16/22] KVM: ARM64: Add reset and access handlers for PMUSERENR register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 17/22] KVM: ARM64: Add reset and access handlers for PMSWINC register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 18/22] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 19/22] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 20/22] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 21/22] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 22/22] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-14 11:53 ` [PATCH v2 00/22] KVM: ARM64: Add guest PMU support Christoffer Dall
2015-09-14 11:53 ` Christoffer Dall
2015-09-14 12:58 ` Shannon Zhao
2015-09-14 12:58 ` Shannon Zhao
2015-09-14 13:24 ` Shannon Zhao
2015-09-14 13:24 ` Shannon Zhao
2015-09-16 21:07 ` Wei Huang
2015-09-16 21:07 ` Wei Huang
2015-09-17 1:32 ` Shannon Zhao
2015-09-17 1:32 ` Shannon Zhao
2015-09-17 5:56 ` Wei Huang
2015-09-17 5:56 ` Wei Huang
2015-09-17 6:47 ` Shannon Zhao
2015-09-17 6:47 ` Shannon Zhao
2015-09-17 6:47 ` Shannon Zhao
2015-09-17 9:30 ` Andrew Jones
2015-09-17 9:30 ` Andrew Jones
2015-09-17 9:35 ` Shannon Zhao
2015-09-17 9:35 ` Shannon Zhao
2015-09-17 9:35 ` Shannon Zhao
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