From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 04/22] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register
Date: Mon, 14 Sep 2015 13:11:37 +0100 [thread overview]
Message-ID: <55F6B979.3010006@arm.com> (raw)
In-Reply-To: <55F63B87.4020205@huawei.com>
On 14/09/15 04:14, Shannon Zhao wrote:
>
>
> On 2015/9/11 18:07, Marc Zyngier wrote:
>> On 11/09/15 09:54, Shannon Zhao wrote:
>>>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>>>
>>>> Add reset handler which gets host value of PMCR_EL0 and make writable
>>>> bits architecturally UNKNOWN. Add a common access handler for PMU
>>>> registers which emulates writing and reading register and add emulation
>>>> for PMCR.
>>>>
>>>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>>>> ---
>>>> arch/arm64/kvm/sys_regs.c | 76 +++++++++++++++++++++++++++++++++++++++++++++--
>>>> 1 file changed, 74 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>>>> index c370b40..db1be44 100644
>>>> --- a/arch/arm64/kvm/sys_regs.c
>>>> +++ b/arch/arm64/kvm/sys_regs.c
>>>> @@ -33,6 +33,7 @@
>>>> #include <asm/kvm_emulate.h>
>>>> #include <asm/kvm_host.h>
>>>> #include <asm/kvm_mmu.h>
>>>> +#include <asm/pmu.h>
>>>>
>>>> #include <trace/events/kvm.h>
>>>>
>>>> @@ -236,6 +237,48 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>>>> vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
>>>> }
>>>>
>>>> +static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>>>> +{
>>>> + u32 pmcr;
>>>> +
>>>> + asm volatile("mrs %0, pmcr_el0\n" : "=r" (pmcr));
>>>> + /* Writable bits of PMCR_EL0 (ARMV8_PMCR_MASK) is reset to UNKNOWN*/
>>>> + if (!vcpu_mode_is_32bit(vcpu))
>>>> + vcpu_sys_reg(vcpu, r->reg) = (pmcr & ~ARMV8_PMCR_MASK)
>>>> + | (ARMV8_PMCR_MASK & 0xdecafbad);
>>>> + else
>>>> + vcpu_cp15(vcpu, r->reg) = (pmcr & ~ARMV8_PMCR_MASK)
>>>> + | (ARMV8_PMCR_MASK & 0xdecafbad);
>> I have some concerns about blindly reusing the top bits of the host's
>> PMCR_EL0 register, specially when it comes to the PMCR_EL0.N. Given that
>> we're fully emulating the PMU, shouldn't we simply define how many
>> counters we're emulating?
>>
>
> But how many counters should we define? And what does this definition
> based on? The only gist I think is the number of counters on host. And
> what's the reason to define less or more than PMCR_EL0.N? I didn't find
> one. So I choose to be consistent with host.
The problem is that choosing the host value may be just the wrong thing
once you migrate it. It is not a big deal, but it is worth keeping it in
mind. it should anyway be possible to size the PMU from userspace,
overriding the value you've selected at reset.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <marc.zyngier@arm.com>
To: Shannon Zhao <zhaoshenglong@huawei.com>, kvmarm@lists.cs.columbia.edu
Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
christoffer.dall@linaro.org, will.deacon@arm.com,
alex.bennee@linaro.org, wei@redhat.com, shannon.zhao@linaro.org,
peter.huangpeng@huawei.com
Subject: Re: [PATCH v2 04/22] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register
Date: Mon, 14 Sep 2015 13:11:37 +0100 [thread overview]
Message-ID: <55F6B979.3010006@arm.com> (raw)
In-Reply-To: <55F63B87.4020205@huawei.com>
On 14/09/15 04:14, Shannon Zhao wrote:
>
>
> On 2015/9/11 18:07, Marc Zyngier wrote:
>> On 11/09/15 09:54, Shannon Zhao wrote:
>>>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>>>
>>>> Add reset handler which gets host value of PMCR_EL0 and make writable
>>>> bits architecturally UNKNOWN. Add a common access handler for PMU
>>>> registers which emulates writing and reading register and add emulation
>>>> for PMCR.
>>>>
>>>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>>>> ---
>>>> arch/arm64/kvm/sys_regs.c | 76 +++++++++++++++++++++++++++++++++++++++++++++--
>>>> 1 file changed, 74 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>>>> index c370b40..db1be44 100644
>>>> --- a/arch/arm64/kvm/sys_regs.c
>>>> +++ b/arch/arm64/kvm/sys_regs.c
>>>> @@ -33,6 +33,7 @@
>>>> #include <asm/kvm_emulate.h>
>>>> #include <asm/kvm_host.h>
>>>> #include <asm/kvm_mmu.h>
>>>> +#include <asm/pmu.h>
>>>>
>>>> #include <trace/events/kvm.h>
>>>>
>>>> @@ -236,6 +237,48 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>>>> vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
>>>> }
>>>>
>>>> +static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>>>> +{
>>>> + u32 pmcr;
>>>> +
>>>> + asm volatile("mrs %0, pmcr_el0\n" : "=r" (pmcr));
>>>> + /* Writable bits of PMCR_EL0 (ARMV8_PMCR_MASK) is reset to UNKNOWN*/
>>>> + if (!vcpu_mode_is_32bit(vcpu))
>>>> + vcpu_sys_reg(vcpu, r->reg) = (pmcr & ~ARMV8_PMCR_MASK)
>>>> + | (ARMV8_PMCR_MASK & 0xdecafbad);
>>>> + else
>>>> + vcpu_cp15(vcpu, r->reg) = (pmcr & ~ARMV8_PMCR_MASK)
>>>> + | (ARMV8_PMCR_MASK & 0xdecafbad);
>> I have some concerns about blindly reusing the top bits of the host's
>> PMCR_EL0 register, specially when it comes to the PMCR_EL0.N. Given that
>> we're fully emulating the PMU, shouldn't we simply define how many
>> counters we're emulating?
>>
>
> But how many counters should we define? And what does this definition
> based on? The only gist I think is the number of counters on host. And
> what's the reason to define less or more than PMCR_EL0.N? I didn't find
> one. So I choose to be consistent with host.
The problem is that choosing the host value may be just the wrong thing
once you migrate it. It is not a big deal, but it is worth keeping it in
mind. it should anyway be possible to size the PMU from userspace,
overriding the value you've selected at reset.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2015-09-14 12:11 UTC|newest]
Thread overview: 113+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-11 8:54 [PATCH v2 00/22] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` [PATCH v2 01/22] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` [PATCH v2 02/22] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 9:10 ` Marc Zyngier
2015-09-11 9:10 ` Marc Zyngier
2015-09-11 9:58 ` Shannon Zhao
2015-09-11 9:58 ` Shannon Zhao
2015-09-11 9:58 ` Shannon Zhao
2015-09-11 8:54 ` [PATCH v2 03/22] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` [PATCH v2 04/22] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 10:07 ` Marc Zyngier
2015-09-11 10:07 ` Marc Zyngier
2015-09-14 3:14 ` Shannon Zhao
2015-09-14 3:14 ` Shannon Zhao
2015-09-14 3:14 ` Shannon Zhao
2015-09-14 12:11 ` Marc Zyngier [this message]
2015-09-14 12:11 ` Marc Zyngier
2015-09-11 8:54 ` [PATCH v2 05/22] KVM: ARM64: Add a helper for CP15 registers reset to UNKNOWN Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 10:16 ` Marc Zyngier
2015-09-11 10:16 ` Marc Zyngier
2015-09-11 10:17 ` Marc Zyngier
2015-09-11 10:17 ` Marc Zyngier
2015-09-11 8:54 ` [PATCH v2 06/22] KVM: ARM64: Add reset and access handlers for PMSELR register Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:54 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 07/22] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 10:27 ` Marc Zyngier
2015-09-11 10:27 ` Marc Zyngier
2015-09-11 8:55 ` [PATCH v2 08/22] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 11:04 ` Marc Zyngier
2015-09-11 11:04 ` Marc Zyngier
2015-09-11 13:35 ` Shannon Zhao
2015-09-11 13:35 ` Shannon Zhao
2015-09-11 14:14 ` Marc Zyngier
2015-09-11 14:14 ` Marc Zyngier
2015-09-11 8:55 ` [PATCH v2 09/22] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 10/22] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 11/22] KVM: ARM64: Add reset and access handlers for PMCCNTR register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 12/22] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 13/22] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 14/22] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 15/22] KVM: ARM64: Add a helper for CP15 registers reset to specified value Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 16/22] KVM: ARM64: Add reset and access handlers for PMUSERENR register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 17/22] KVM: ARM64: Add reset and access handlers for PMSWINC register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 18/22] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 19/22] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 20/22] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 21/22] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` [PATCH v2 22/22] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-11 8:55 ` Shannon Zhao
2015-09-14 11:53 ` [PATCH v2 00/22] KVM: ARM64: Add guest PMU support Christoffer Dall
2015-09-14 11:53 ` Christoffer Dall
2015-09-14 12:58 ` Shannon Zhao
2015-09-14 12:58 ` Shannon Zhao
2015-09-14 13:24 ` Shannon Zhao
2015-09-14 13:24 ` Shannon Zhao
2015-09-16 21:07 ` Wei Huang
2015-09-16 21:07 ` Wei Huang
2015-09-17 1:32 ` Shannon Zhao
2015-09-17 1:32 ` Shannon Zhao
2015-09-17 5:56 ` Wei Huang
2015-09-17 5:56 ` Wei Huang
2015-09-17 6:47 ` Shannon Zhao
2015-09-17 6:47 ` Shannon Zhao
2015-09-17 6:47 ` Shannon Zhao
2015-09-17 9:30 ` Andrew Jones
2015-09-17 9:30 ` Andrew Jones
2015-09-17 9:35 ` Shannon Zhao
2015-09-17 9:35 ` Shannon Zhao
2015-09-17 9:35 ` Shannon Zhao
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